From: Reinette Chatre <reinette.chatre@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: tglx@linutronix.de, fenghua.yu@intel.com, tony.luck@intel.com,
kuo-lang.tseng@intel.com, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches
Date: Tue, 6 Aug 2019 11:13:22 -0700 [thread overview]
Message-ID: <d0c04521-ec1a-3468-595c-6929f25f37ff@intel.com> (raw)
In-Reply-To: <20190806173300.GF25897@zn.tnic>
Hi Borislav,
On 8/6/2019 10:33 AM, Borislav Petkov wrote:
> On Tue, Aug 06, 2019 at 09:55:56AM -0700, Reinette Chatre wrote:
>> I am a bit cautious about this. When I started this work I initially
>> added a helper function to resctrl that calls CPUID to determine if the
>> cache is inclusive. At that time I became aware of a discussion
>> motivating against scattered CPUID calls and motivating for one instance
>> of CPUID information:
>> http://lkml.kernel.org/r/alpine.DEB.2.21.1906162141301.1760@nanos.tec.linutronix.de
>
> Ah, there's that. That's still somewhat a work/discussion in progress
> thing. Let me discuss it with tglx.
>
>> To answer your question about checking any cache: this seems to be
>
> I meant the CPUID on any CPU and thus any cache - i.e., all L3s on the
> system should be inclusive and identical in that respect. Can't work
> otherwise, I'd strongly presume.
This is my understanding, yes. While this patch supports knowing whether
each L3 is inclusive or not, I expect this information to be the same
for all L3 instances as will be supported by a single query in
rdt_pseudo_lock_init(). This definitely is the case on the platforms we
are enabling in this round.
>> different between L2 and L3. On the Atom systems where L2 pseudo-locking
>> works well the L2 cache is not inclusive. We are also working on
>> supporting cache pseudo-locking on L3 cache that is not inclusive.
>
> Hmm, so why are you enforcing the inclusivity now:
>
> + if (p->r->cache_level == 3 &&
> + !get_cache_inclusive(plr->cpu, p->r->cache_level)) {
> + rdt_last_cmd_puts("L3 cache not inclusive\n");
>
> but then will remove this requirement in the future? Why are we even
> looking at cache inclusivity then and not make pseudo-locking work
> regardless of that cache property?
Some platforms being enabled in this round have SKUs with inclusive
cache and also SKUs with non-inclusive cache. The non-inclusive cache
SKUs do not support cache pseudo-locking and cannot be made to support
cache pseudo-locking with software changes. Needing to know if cache is
inclusive or not will thus remain a requirement to distinguish between
these different SKUs. Supporting cache pseudo-locking on platforms with
non inclusive cache will require new hardware features.
> Because if we're going to go and model this cache inclusivity property
> properly in struct cpuinfo_x86 or struct cacheinfo or wherever, and do
> that for all cache levels because apparently we're going to need that;
> but then later it turns out we won't need it after all, why are we even
> bothering?
>
> Or am I missing some aspect?
Reinette
next prev parent reply other threads:[~2019-08-06 18:19 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 17:29 [PATCH V2 00/10] x86/CPU and x86/resctrl: Support pseudo-lock regions spanning L2 and L3 cache Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches Reinette Chatre
2019-08-02 18:03 ` Borislav Petkov
2019-08-02 20:11 ` Reinette Chatre
2019-08-03 9:44 ` Borislav Petkov
2019-08-05 17:57 ` Reinette Chatre
2019-08-06 15:57 ` Borislav Petkov
2019-08-06 16:55 ` Reinette Chatre
2019-08-06 17:33 ` Borislav Petkov
2019-08-06 18:13 ` Reinette Chatre [this message]
2019-08-06 18:33 ` Borislav Petkov
2019-08-06 18:53 ` Reinette Chatre
2019-08-06 19:16 ` Borislav Petkov
2019-08-06 20:22 ` Reinette Chatre
2019-08-06 20:40 ` Borislav Petkov
2019-08-06 21:16 ` Reinette Chatre
2019-08-08 8:08 ` Borislav Petkov
2019-08-08 8:13 ` Borislav Petkov
2019-08-08 20:08 ` Reinette Chatre
2019-08-09 7:33 ` Borislav Petkov
2019-08-09 16:18 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 02/10] x86/resctrl: Remove unnecessary size compute Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 03/10] x86/resctrl: Constrain C-states during pseudo-lock region init Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 04/10] x86/resctrl: Set cache line size using new utility Reinette Chatre
2019-08-05 15:57 ` Borislav Petkov
2019-07-30 17:29 ` [PATCH V2 05/10] x86/resctrl: Associate pseudo-locked region's cache instance by id Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 06/10] x86/resctrl: Introduce utility to return pseudo-locked cache portion Reinette Chatre
2019-08-05 16:07 ` Borislav Petkov
2019-07-30 17:29 ` [PATCH V2 07/10] x86/resctrl: Remove unnecessary pointer to pseudo-locked region Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 08/10] x86/resctrl: Support pseudo-lock regions spanning resources Reinette Chatre
2019-08-07 9:18 ` Borislav Petkov
2019-08-07 19:07 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 09/10] x86/resctrl: Pseudo-lock portions of multiple resources Reinette Chatre
2019-08-07 15:25 ` Borislav Petkov
2019-08-07 19:23 ` Reinette Chatre
2019-08-08 8:44 ` Borislav Petkov
2019-08-08 20:13 ` Reinette Chatre
2019-08-09 7:38 ` Borislav Petkov
2019-08-09 16:20 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 10/10] x86/resctrl: Only pseudo-lock L3 cache when inclusive Reinette Chatre
2019-07-30 20:00 ` [PATCH V2 00/10] x86/CPU and x86/resctrl: Support pseudo-lock regions spanning L2 and L3 cache Thomas Gleixner
2019-07-30 20:10 ` Reinette Chatre
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