From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC5E6C11F66 for ; Wed, 14 Jul 2021 14:38:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A174B613C0 for ; Wed, 14 Jul 2021 14:38:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232312AbhGNOk6 (ORCPT ); Wed, 14 Jul 2021 10:40:58 -0400 Received: from foss.arm.com ([217.140.110.172]:35658 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231977AbhGNOk5 (ORCPT ); Wed, 14 Jul 2021 10:40:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9951C31B; Wed, 14 Jul 2021 07:38:05 -0700 (PDT) Received: from [10.57.36.240] (unknown [10.57.36.240]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CBDF53F694; Wed, 14 Jul 2021 07:38:03 -0700 (PDT) Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU To: Oliver Graute , shawnguo@kernel.org Cc: devicetree@vger.kernel.org, aisheng.dong@nxp.com, fabio.estevam@nxp.com, Rob Herring , Sascha Hauer , Sascha Hauer , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210714120925.23571-1-oliver.graute@kococonnector.com> <20210714120925.23571-3-oliver.graute@kococonnector.com> From: Robin Murphy Message-ID: Date: Wed, 14 Jul 2021 15:37:58 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210714120925.23571-3-oliver.graute@kococonnector.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-07-14 13:09, Oliver Graute wrote: > added node for System MMU Note that it's a bit of a dangerous game to enable an SMMU without the complete Stream ID topology for *all* its upstream devices also described, since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin peoples' day. It might be more polite to add it in a disabled state until every "iommus" property has been filled in, so that people who do want to play with it for specific devices in the meantime can easily just flip the status (while taking the necessary precautions), but people who don't care won't be inadvertently affected regardless of their kernel config. I'm assuming an SMMU with 32 contexts has more than a single USB controller behind it... Robin. > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Fabio Estevam > Cc: Dong Aisheng > > Signed-off-by: Oliver Graute > --- > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > index 7efc0add74ea..fa827ed04e09 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -140,6 +140,23 @@ > method = "smc"; > }; > > + smmu: iommu@51400000 { > + compatible = "arm,mmu-500"; > + interrupt-parent = <&gic>; > + reg = <0 0x51400000 0 0x40000>; > + #global-interrupts = <1>; > + #iommu-cells = <2>; > + interrupts = <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; > + }; > + > timer { > compatible = "arm,armv8-timer"; > interrupts = , /* Physical Secure */ >