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Wed, 9 Jun 2021 05:26:54 +0000 Received: from [10.25.75.134] (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Jun 2021 05:26:51 +0000 Subject: Re: Query regarding the use of pcie-designware-plat.c file To: Gustavo Pimentel , "lorenzo.pieralisi@arm.com" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "amurray@thegoodpenguin.co.uk" , "jingoohan1@gmail.com" , Joao Pinto CC: Jonathan Hunter , Thierry Reding , Krishna Thota , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <34650ed1-6567-3c8f-fe29-8816f0fd74f2@nvidia.com> From: Vidya Sagar Message-ID: Date: Wed, 9 Jun 2021 10:56:48 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fc6f78ba-5d24-47fb-d24a-08d92b07314a X-MS-TrafficTypeDiagnostic: DM6PR12MB3964: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2021 05:26:54.0298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc6f78ba-5d24-47fb-d24a-08d92b07314a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3964 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/9/2021 2:47 AM, Gustavo Pimentel wrote: > External email: Use caution opening links or attachments > > > Hi Vidya, > > The pcie-designware-plat.c is the driver for the Synopsys PCIe RC IP > prototype. Thanks for the info Gustavo. But, I don't see any DT file having only "snps,dw-pcie" compatibility string. All the DT files that have "snps,dw-pci" compatibility string also have their platform specific compatibility string and their respective host controller drivers. Also, it is the platform specific compatibility string that is used for binding purpose with their respective drivers and not the "snps,dw-pcie". So, wondering when will pcie-designware-plat.c be used as there is not DT file which has only "snps,dw-pcie" as the compatibility string. - Vidya Sagar > > -Gustavo > > On Tue, Jun 8, 2021 at 20:22:37, Vidya Sagar wrote: > >> Hi, >> I would like to know what is the use of pcie-designware-plat.c file. >> This looks like a skeleton file and can't really work with any specific >> hardware as such. >> Some context for this mail thread is, if the config CONFIG_PCIE_DW_PLAT >> is enabled in a system where a Synopsys DesignWare IP based PCIe >> controller is present and its configuration is enabled (Ex:- Tegra194 >> system with CONFIG_PCIE_TEGRA194_HOST enabled), then, it can so happen >> that the probe of pcie-designware-plat.c called first (because all DWC >> based PCIe controller nodes have "snps,dw-pcie" compatibility string) >> and can crash the system. >> One solution to this issue is to remove the "snps,dw-pcie" from the >> compatibility string (as was done through the commit f9f711efd441 >> ("arm64: tegra: Fix Tegra194 PCIe compatible string") but it seems like >> a localized fix for Tegra194 where the issue potentially is global, as >> in, the crash can happen on any platform. >> So, wondering if the config option CONFIG_PCIE_DW_PLAT can be removed >> altogether for pcie-designware-plat.c? >> >> Thanks, >> Vidya Sagar > >