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[2001:1c00:c0c:fe00:7e79:4dac:39d0:9c14]) by smtp.gmail.com with ESMTPSA id y20sm6009145wmi.25.2019.12.12.06.34.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2019 06:34:35 -0800 (PST) Subject: Re: [PATCH 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight To: Lee Jones Cc: Maarten Lankhorst , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , linux-acpi@vger.kernel.org, intel-gfx , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20191119151818.67531-1-hdegoede@redhat.com> <20191119151818.67531-3-hdegoede@redhat.com> <20191210085111.GQ3468@dell> <20191212084546.GA3468@dell> From: Hans de Goede Message-ID: Date: Thu, 12 Dec 2019 15:34:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191212084546.GA3468@dell> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 12-12-2019 09:45, Lee Jones wrote: > On Wed, 11 Dec 2019, Hans de Goede wrote: > >> Hi Lee, >> >> On 10-12-2019 09:51, Lee Jones wrote: >>> On Tue, 19 Nov 2019, Hans de Goede wrote: >>> >>>> At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2 >>>> different PWM controllers for controlling the LCD's backlight brightness. >>>> >>>> Either the one integrated into the PMIC or the one integrated into the >>>> SoC (the 1st LPSS PWM controller). >>>> >>>> So far in the LPSS code on BYT we have skipped registering the LPSS PWM >>>> controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is >>>> present, assuming that in this case the PMIC PWM controller will be used. >>>> >>>> On CHT we have been relying on only 1 of the 2 PWM controllers being >>>> enabled in the DSDT at the same time; and always registered the lookup. >>>> >>>> So far this has been working, but the correct way to determine which PWM >>>> controller needs to be used is by checking a bit in the VBT table and >>>> recently I've learned about 2 different BYT devices: >>>> Point of View MOBII TAB-P800W >>>> Acer Switch 10 SW5-012 >>>> >>>> Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS >>>> PWM controller (and the VBT correctly indicates this), so here our old >>>> heuristics fail. >>>> >>>> Since only the i915 driver has access to the VBT, this commit renames >>>> the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM >>>> controller to "pwm_pmic_backlight" so that the i915 driver can do a >>>> pwm_get() for the right controller depending on the VBT bit, instead of >>>> the i915 driver relying on a "pwm_backlight" lookup getting registered >>>> which magically points to the right controller. >>>> >>>> Signed-off-by: Hans de Goede >>>> --- >>>> drivers/mfd/intel_soc_pmic_core.c | 2 +- >>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> For my own reference: >>> Acked-for-MFD-by: Lee Jones >> >> As mentioned in the cover-letter, to avoid breaking bi-sectability >> as well as to avoid breaking the intel-gfx CI we need to merge this series >> in one go through one tree. Specifically through the drm-intel tree. >> Is that ok with you ? >> >> If this is ok with you, then you do not have to do anything, I will just push >> the entire series to drm-intel. drivers/mfd/intel_soc_pmic_core.c >> does not see much changes so I do not expect this to lead to any conflicts. > > It's fine, so long as a minimal immutable pull-request is provided. > Whether it's pulled or not will depend on a number of factors, but it > needs to be an option. The way the drm subsys works that is not really a readily available option. The struct definition which this patch changes a single line in has not been touched since 2015-06-26 so I really doubt we will get a conflict from this. Regards, Hans