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[91.79.162.197]) by smtp.googlemail.com with ESMTPSA id j25sm483692lfh.6.2019.06.14.06.02.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Jun 2019 06:02:26 -0700 (PDT) Subject: Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check To: Bitan Biswas , Laxman Dewangan , Thierry Reding , Jonathan Hunter , linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Rosin , Wolfram Sang Cc: Shardar Mohammed , Sowjanya Komatineni , Mantravadi Karthik References: <1560250274-18499-1-git-send-email-bbiswas@nvidia.com> <1560250274-18499-6-git-send-email-bbiswas@nvidia.com> <42ce2523-dab9-0cdf-e8ff-42631dd161b7@gmail.com> <78140337-dca0-e340-a501-9e37eca6cc87@nvidia.com> <9cb7123a-1ebd-3a93-60dc-c8f57f60270b@gmail.com> From: Dmitry Osipenko Message-ID: Date: Fri, 14 Jun 2019 16:02:25 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 14.06.2019 12:50, Bitan Biswas пишет: > > > On 6/13/19 5:28 AM, Dmitry Osipenko wrote: >> 13.06.2019 14:30, Bitan Biswas пишет: >>> >>> >>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote: >>>> 11.06.2019 13:51, Bitan Biswas пишет: >>>>> Fix expression for residual bytes(less than word) transfer >>>>> in I2C PIO mode RX/TX. >>>>> >>>>> Signed-off-by: Bitan Biswas >>>>> --- >>>> >>>> [snip] >>>> >>>>>            /* >>>>> -         * Update state before writing to FIFO.  If this casues us >>>>> +         * Update state before writing to FIFO.  If this causes us >>>>>             * to finish writing all bytes (AKA buf_remaining goes to >>>>> 0) we >>>>>             * have a potential for an interrupt (PACKET_XFER_COMPLETE is >>>>> -         * not maskable).  We need to make sure that the isr sees >>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly. >>>>> +         * not maskable). >>>>>             */ >>>>>            buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; >>>> >>>> Looks like the comment could be removed altogether because it doesn't >>>> make sense since interrupt handler is under xfer_lock which is kept >>>> locked during of tegra_i2c_xfer_msg(). >>> I would push a separate patch to remove this comment because of >>> xfer_lock in ISR now. >>> >>>> >>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable", >>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does? >>>> >>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips >>> newer than Tegra30 allows one to not see interrupt after Packet transfer >>> complete. With the xfer_lock in ISR the scenario discussed in comment >>> can be ignored. >> >> Also note that xfer_lock could be removed and replaced with a just >> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care >> about IRQ not firing during of the preparation process. > This should need sufficient testing hence let us do it in a different series. I don't think that there is much to test here since obviously it should work. >> >> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all >> IRQ's could be simply unmasked during the driver's probe, in that case >> it may worth to add a kind of "in-progress" flag to catch erroneous >> interrupts. >> > TX interrupt needs special handling if this change is done. Hence I think it should be > taken up after sufficient testing in a separate patch. This one is indeed a bit more trickier. Probably another alternative could be to keep GIC interrupt disabled while no transfer is performed, then you'll have to request interrupt in a disabled state using IRQ_NOAUTOEN flag. And yes, that all should be a separate changes if you're going to implement them.