Re: [RESEND PATCH] arm64: v8.4: Support for new floating point multiplication variant

From: gengdongjiu <gengdongjiu@huawei.com>
To: Dave Martin <Dave.Martin@arm.com>
Cc: Mark Rutland <Mark.Rutland@arm.com>,
	"guohanjun@huawei.com" <guohanjun@huawei.com>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>,
	"Catalin Marinas" <Catalin.Marinas@arm.com>,
	"corbet@lwn.net" <corbet@lwn.net>,
	"Will Deacon" <Will.Deacon@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linuxarm@huawei.com" <linuxarm@huawei.com>,
	"zhihui.gao@huawei.com" <zhihui.gao@huawei.com>,
	"huangshaoyu@huawei.com" <huangshaoyu@huawei.com>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"arvind.yadav.cs@gmail.com" <arvind.yadav.cs@gmail.com>,
	Robin Murphy <Robin.Murphy@arm.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"zhanghaibin7@huawei.com" <zhanghaibin7@huawei.com>
Subject: Re: [RESEND PATCH] arm64: v8.4: Support for new floating point multiplication variant
Date: Tue, 12 Dec 2017 09:44:06 +0800	[thread overview]
Message-ID: <d39500ed-0d17-a8b2-b7e2-9e48b5d8d43a@huawei.com> (raw)
In-Reply-To: <20171211132914.GJ22781@e103592.cambridge.arm.com>


On 2017/12/11 21:29, Dave Martin wrote:
>> Thanks for the point out.
>> In fact, this feature only adds two instructions:
>> FP16 * FP16 + FP32
>> FP16 * FP16 - FP32
>>
>> The spec call this bit to ID_AA64ISAR0_EL1.FHM, I do not know why it
>> will call "FHM", I  think call it "FMLXL" may be better, which can
>> stand for FMLAL/FMLSL instructions.
> Although "FHM" is cryptic, I think it makes sense to keep this as "FHM"
> to match the ISAR0 field name -- we've tended to follow this policy
> for other extension names unless there's a much better or more obvious
> name available
Agree with you, I also think the "FHM" is better.

> 
> For "FMLXL", new instructions might be added in the future that match
> the same pattern, and then "FMLXL" could become ambiguous.  So maybe
> this is not the best choice.
Ok.

> 
>>> Maybe something like "widening half-precision floating-point multiply
>>> accumulate" is acceptable wording consistent with the existing
>>> architecture, but I just made that up, so it's not official ;)
>> how about something like "performing a multiplication of each FP16
>> element of one vector with the corresponding FP16 element of a second
>> vector, and to add or subtract this without an intermediate rounding
>> to the corresponding FP32 element in a third vector."?
> We could have that, I guess.
Ok, thanks!

> 
>>>> instructions set. Let the userspace know about it via a
>>>> HWCAP bit and MRS emulation.