From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932260AbcISSEP (ORCPT ); Mon, 19 Sep 2016 14:04:15 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53154 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752829AbcISSEN (ORCPT ); Mon, 19 Sep 2016 14:04:13 -0400 Subject: Re: [PATCH 05/61] perf tools: Introduce c2c_decode_stats function To: Nilay Vaish , Jiri Olsa References: <1474290610-23241-1-git-send-email-jolsa@kernel.org> <1474290610-23241-6-git-send-email-jolsa@kernel.org> Cc: Arnaldo Carvalho de Melo , lkml , Don Zickus , Ingo Molnar , Peter Zijlstra , Namhyung Kim , David Ahern , Andi Kleen From: Joe Mario Message-ID: Date: Mon, 19 Sep 2016 14:04:10 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 19 Sep 2016 18:04:13 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/19/2016 01:15 PM, Nilay Vaish wrote: > On 19 September 2016 at 08:09, Jiri Olsa wrote: >> diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h >> index 7f69bf9d789d..27c6bb5abafb 100644 >> --- a/tools/perf/util/mem-events.h >> +++ b/tools/perf/util/mem-events.h >> @@ -2,6 +2,10 @@ >> #define __PERF_MEM_EVENTS_H >> >> #include >> +#include >> +#include >> +#include >> +#include "stat.h" >> >> struct perf_mem_event { >> bool record; >> @@ -33,4 +37,36 @@ int perf_mem__lck_scnprintf(char *out, size_t sz, struct mem_info *mem_info); >> >> int perf_script__meminfo_scnprintf(char *bf, size_t size, struct mem_info *mem_info); >> >> +struct c2c_stats { >> + int nr_entries; >> + >> + int locks; /* count of 'lock' transactions */ >> + int store; /* count of all stores in trace */ >> + int st_uncache; /* stores to uncacheable address */ >> + int st_noadrs; /* cacheable store with no address */ > > No address! Why would that happen? [Resending without the html] There are a small number of instructions that will trigger a perf mem event and will have no address associated with them. Three of them include mfence, wrmsr, and rdtsc. I believe there are at least two more. > > > -- > Nilay >