From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754894AbbCEJfA (ORCPT ); Thu, 5 Mar 2015 04:35:00 -0500 Received: from mail-bl2on0055.outbound.protection.outlook.com ([65.55.169.55]:46144 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754711AbbCEJey (ORCPT ); Thu, 5 Mar 2015 04:34:54 -0500 From: Appana Durga Kedareswara Rao To: Paul Bolle CC: "dan.j.williams@intel.com" , "vinod.koul@intel.com" , Michal Simek , Soren Brinkmann , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anirudha Sarangi , Srikanth Vemula , Srikanth Thokala Subject: RE: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine driver support Thread-Topic: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine driver support Thread-Index: AQHQVTRjDG14Fmm17k+IY/uXMpxS0p0Nn8OQ Date: Thu, 5 Mar 2015 09:34:46 +0000 References: <6f3b34935c0f405199cacd5312e972ac@BN1BFFO11FD017.protection.gbl> <1425333669.24292.124.camel@x220> In-Reply-To: <1425333669.24292.124.camel@x220> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.97.163] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-7.5.0.1018-21376.004 X-TM-AS-User-Approved-Sender: Yes;Yes;Yes Message-ID: X-EOPAttributedMessage: 0 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=appana.durga.rao@xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;BMV:0;SFV:NSPM;SFS:(10009020)(6009001)(438002)(199003)(189002)(24454002)(51704005)(377424004)(52604005)(377454003)(13464003)(74316001)(47776003)(33646002)(106466001)(50466002)(53416004)(76176999)(50986999)(46102003)(54356999)(106116001)(110136001)(6806004)(92566002)(77156002)(62966003)(108616004)(86362001)(23676002)(102836002)(19580405001)(92726002)(19580395003)(104016003)(5890100001)(2656002)(2950100001)(87936001)(107986001)(24736002);DIR:OUT;SFP:1101;SCL:1;SRVR:BN1BFFO11HUB005;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1BFFO11HUB005; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5001007)(5005006);SRVR:BN1BFFO11HUB005;BCL:0;PCL:0;RULEID:;SRVR:BN1BFFO11HUB005; X-Forefront-PRVS: 05066DEDBB X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2015 09:34:51.4939 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1BFFO11HUB005 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id t259Z6NA018475 Hi Paul Bolle, Thanks for reviewing the patch > -----Original Message----- > From: Paul Bolle [mailto:pebolle@tiscali.nl] > Sent: Tuesday, March 03, 2015 3:31 AM > To: Appana Durga Kedareswara Rao > Cc: dan.j.williams@intel.com; vinod.koul@intel.com; Michal Simek; Soren > Brinkmann; dmaengine@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Appana Durga > Kedareswara Rao; Anirudha Sarangi; Srikanth Vemula; Srikanth Thokala > Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine > driver support > > On Mon, 2015-03-02 at 23:25 +0530, Kedareswara rao Appana wrote: > > --- a/drivers/dma/Kconfig > > +++ b/drivers/dma/Kconfig > > @@ -425,6 +425,19 @@ config IMG_MDC_DMA > > help > > Enable support for the IMG multi-threaded DMA controller (MDC). > > > > +config XILINX_DMA > > + tristate "Xilinx AXI DMA Engine" > > + depends on (ARCH_ZYNQ || MICROBLAZE) > > + select DMA_ENGINE > > + help > > + Enable support for Xilinx AXI DMA Soft IP. > > + > > + This engine provides high-bandwidth direct memory access > > + between memory and AXI4-Stream type target peripherals. > > + It has two stream interfaces/channels, Memory Mapped to > > + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the > > + data transfers. > > + > > How did you test this patch? On next-20150302, running x86_64, I got: > > $ make ARCH=microblaze menuconfig > HOSTCC scripts/basic/fixdep > HOSTCC scripts/kconfig/mconf.o > SHIPPED scripts/kconfig/zconf.tab.c > SHIPPED scripts/kconfig/zconf.lex.c > HOSTCC scripts/kconfig/zconf.tab.o > HOSTCC scripts/kconfig/lxdialog/checklist.o > HOSTCC scripts/kconfig/lxdialog/util.o > HOSTCC scripts/kconfig/lxdialog/inputbox.o > HOSTCC scripts/kconfig/lxdialog/textbox.o > HOSTCC scripts/kconfig/lxdialog/yesno.o > HOSTCC scripts/kconfig/lxdialog/menubox.o > HOSTLD scripts/kconfig/mconf > scripts/kconfig/mconf Kconfig > drivers/dma/Kconfig:436: syntax error > drivers/dma/Kconfig:435: unknown option "This" > drivers/dma/Kconfig:436: unknown option "between" > drivers/dma/Kconfig:437: unknown option "It" > drivers/dma/Kconfig:438: unknown option "Stream" > drivers/dma/Kconfig:439: unknown option "data" > make[1]: *** [menuconfig] Error 1 > make: *** [menuconfig] Error 2 > > Caused by the invalid indentation used here. You should add two spaces > after the initial tab in lines 436 through 439. > My Bad I forgot to compile the patch before I sent to the open source. Will fix this in the next version of the patch. Regards, Kedar. > > Paul Bolle This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I