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From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
To: Will Deacon <will@kernel.org>,
	Guangbin Huang <huangguangbin2@huawei.com>
Cc: <davem@davemloft.net>, <kuba@kernel.org>,
	<catalin.marinas@arm.com>, <maz@kernel.org>,
	<mark.rutland@arm.com>, <dbrazdil@google.com>,
	<qperret@google.com>, <netdev@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <lipeng321@huawei.com>,
	<peterz@infradead.org>
Subject: Re: Re: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately
Date: Fri, 15 Oct 2021 09:48:16 +0800	[thread overview]
Message-ID: <d5f6f22b-3426-a114-cb76-97019ae44c97@huawei.com> (raw)
In-Reply-To: <20210730090056.GA22968@willie-the-truck>

Hi, Will

On 2021/7/30 17:00, Will Deacon wrote:
> Hi,
> 
> On Fri, Jul 30, 2021 at 11:14:22AM +0800, Guangbin Huang wrote:
>> From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
>>
>> Device registers can be mapped as write-combine type. In this case, data
>> are not written into the device immediately. They are temporarily stored
>> in the write combine buffer and written into the device when the buffer
>> is full. But in some situation, we need to flush the write combine
>> buffer to device immediately for better performance. So we add a general
>> function called 'flush_wc_write()'. We use DGH instruction to implement
>> this function for ARM64.
>>
>> Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
>> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
>> ---
>>  arch/arm64/include/asm/io.h | 2 ++
>>  include/linux/io.h          | 6 ++++++
>>  2 files changed, 8 insertions(+)
> 
> -ENODOCUMENTATION
> 
>> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
>> index 7fd836bea7eb..5315d023b2dd 100644
>> --- a/arch/arm64/include/asm/io.h
>> +++ b/arch/arm64/include/asm/io.h
>> @@ -112,6 +112,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
>>  #define __iowmb()		dma_wmb()
>>  #define __iomb()		dma_mb()
>>  
>> +#define flush_wc_write()	dgh()
> 
> I think it would be worthwhile to look at what architectures other than
> arm64 offer here. For example, is there anything similar to this on riscv,
> x86 or power? Doing a quick survery of what's out there might help us define
> a macro that can be used across multiple architectures.

I searched in 'barrier.h' of different architectures and didn't find similar
merge preventing instructions. Could you give me some advice on naming this
common interface ?

Thanks,
Xiongfeng

> 
> Thanks,
> 
> Will
> 
>>  /*
>>   * Relaxed I/O memory access primitives. These follow the Device memory
>>   * ordering rules but do not guarantee any ordering relative to Normal memory
>> diff --git a/include/linux/io.h b/include/linux/io.h
>> index 9595151d800d..469d53444218 100644
>> --- a/include/linux/io.h
>> +++ b/include/linux/io.h
>> @@ -166,4 +166,10 @@ static inline void arch_io_free_memtype_wc(resource_size_t base,
>>  }
>>  #endif
>>  
>> +/* IO barriers */
>> +
>> +#ifndef flush_wc_write
>> +#define flush_wc_write()		do { } while (0)
>> +#endif
>> +
>>  #endif /* _LINUX_IO_H */
>> -- 
>> 2.8.1
>>
> .
> 

  parent reply	other threads:[~2021-10-15  1:48 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  3:14 [PATCH net-next 0/4] net: hns3: add support for TX push Guangbin Huang
2021-07-30  3:14 ` [PATCH net-next 1/4] arm64: barrier: add DGH macros to control memory accesses merging Guangbin Huang
2021-07-30  9:39   ` Catalin Marinas
2021-07-30  3:14 ` [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Guangbin Huang
2021-07-30  9:00   ` Will Deacon
2021-10-11 13:37     ` huangguangbin (A)
2021-10-15  1:48     ` Xiongfeng Wang [this message]
2021-07-30  9:42   ` Catalin Marinas
2021-07-30  3:14 ` [PATCH net-next 3/4] net: hns3: add support for TX push mode Guangbin Huang
2021-07-30  3:14 ` [PATCH net-next 4/4] net: hns3: add ethtool priv-flag for TX push Guangbin Huang

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