From: Steven Price <steven.price@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/2] arm64: Combine workarounds for speculative AT errata
Date: Wed, 13 Nov 2019 14:29:06 +0000 [thread overview]
Message-ID: <d66a3b7f-0338-ca70-7a98-b95aba64221a@arm.com> (raw)
In-Reply-To: <566ecd45c8bf07b3cb5d75a10c9413a8@www.loen.fr>
On 13/11/2019 12:44, Marc Zyngier wrote:
> On 2019-11-13 12:50, Steven Price wrote:
>> Cortex-A57/A72 have a similar errata to Cortex-A76 regarding speculation
>> of the AT instruction. Since the workaround for A57/A72 doesn't require
>> VHE, the restriction enforcing VHE for A76 can be removed by combining
>> the workaround flag for both errata.
>
> Are we sure that A76 behaves the same as A57/A72 when it comes to not
> caching any of the EPD* bits in the TLB? Because the 1319367 workaround
> has a lot of the A72 microarch implicit to it, and I'm not sure this
> works as is on A76 or A55...
Hmm, well I was going purely on the errata documents which have
basically the same text for all the errata. I have to admit I do not
understand the microarch details here. Perhaps it would be better to
leave the VHE and NVHE cases separated then?
Steven
> The patch itself looks OK, but I'd like some reassurance about the
> above.
>
> M.
next prev parent reply other threads:[~2019-11-13 14:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-13 11:41 [PATCH v2 0/2] arm64: Workaround for Cortex-A55 erratum 1530923 Steven Price
2019-11-13 11:41 ` [PATCH v2 1/2] arm64: Combine workarounds for speculative AT errata Steven Price
2019-11-13 12:44 ` Marc Zyngier
2019-11-13 14:29 ` Steven Price [this message]
2019-11-13 14:01 ` Suzuki K Poulose
2019-11-13 14:43 ` Steven Price
2019-11-13 11:41 ` [PATCH v2 2/2] arm64: Workaround for Cortex-A55 erratum 1530923 Steven Price
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