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From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
To: Will Deacon <will@kernel.org>, Vineet Gupta <Vineet.Gupta1@synopsys.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Mark Rutland <mark.rutland@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
	"linux-snps-arc@lists.infradead.org" 
	<linux-snps-arc@lists.infradead.org>
Subject: Re: [RFC] bitops/non-atomic: make @nr unsigned to avoid any DIV
Date: Fri, 6 Aug 2021 19:02:07 +0000	[thread overview]
Message-ID: <d67f12c0-4ede-2a81-9de9-570beb662884@synopsys.com> (raw)
In-Reply-To: <20210806134244.GA2901@willie-the-truck>

On 8/6/21 6:42 AM, Will Deacon wrote:
> On Thu, Aug 05, 2021 at 12:14:08PM -0700, Vineet Gupta wrote:
>> signed math causes generation of costlier instructions such as DIV when
>> they could be done by barrerl shifter.
>>
>> Worse part is this is not caught by things like bloat-o-meter since
>> instruction length / symbols are typically same size.
>>
>> e.g.
>>
>> stock (signed math)
>> __________________
>>
>> 919b4614 <test_taint>:
>> 919b4614:	div	r2,r0,0x20
>>                  ^^^
>> 919b4618:	add2	r2,0x920f6050,r2
>> 919b4620:	ld_s	r2,[r2,0]
>> 919b4622:	lsr	r0,r2,r0
>> 919b4626:	j_s.d	[blink]
>> 919b4628:	bmsk_s	r0,r0,0
>> 919b462a:	nop_s
>>
>> (patched) unsigned math
>> __________________
>>
>> 919b4614 <test_taint>:
>> 919b4614:	lsr	r2,r0,0x5  @nr/32
>>                  ^^^
>> 919b4618:	add2	r2,0x920f6050,r2
>> 919b4620:	ld_s	r2,[r2,0]
>> 919b4622:	lsr	r0,r2,r0     #test_bit()
>> 919b4626:	j_s.d	[blink]
>> 919b4628:	bmsk_s	r0,r0,0
>> 919b462a:	nop_s
> Just FYI, but on arm64 the existing codegen is alright as we have both
> arithmetic and logical shifts.

ARC does too: There's LSR (Logical shift right) and ASR (Arithmetic 
Shift Right).
So perhaps something to be done in the compiler.

>> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
>> ---
>> This is an RFC for feeback, I understand this impacts every arch,
>> but as of now it is only buld/run tested on ARC.
>> ---
>> ---
>>   include/asm-generic/bitops/non-atomic.h | 14 +++++++-------
>>   1 file changed, 7 insertions(+), 7 deletions(-)
> Acked-by: Will Deacon <will@kernel.org>
>
> We should really move test_bit() into the atomic header, but I failed to fix
> the resulting include mess last time I tried that.

OK I'll give it a try too.

  reply	other threads:[~2021-08-06 19:02 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-04 19:15 [PATCH 00/11] ARC atomics update Vineet Gupta
2021-08-04 19:15 ` [PATCH 01/11] ARC: atomics: disintegrate header Vineet Gupta
2021-08-04 19:15 ` [PATCH 02/11] ARC: atomic: !LLSC: remove hack in atomic_set() for for UP Vineet Gupta
2021-08-04 19:15 ` [PATCH 03/11] ARC: atomic: !LLSC: use int data type consistently Vineet Gupta
2021-08-04 19:15 ` [PATCH 04/11] ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return Vineet Gupta
2021-08-04 19:15 ` [PATCH 05/11] ARC: atomics: implement relaxed variants Vineet Gupta
2021-08-04 19:15 ` [PATCH 06/11] ARC: switch to generic bitops Vineet Gupta
2021-08-04 19:15 ` [PATCH 07/11] ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines Vineet Gupta
2021-08-04 19:15 ` [PATCH 08/11] ARC: xchg: !LLSC: remove UP micro-optimization/hack Vineet Gupta
2021-08-04 19:15 ` [PATCH 09/11] ARC: cmpxchg/xchg: rewrite as macros to make type safe Vineet Gupta
2021-08-04 19:15 ` [PATCH 10/11] ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only) Vineet Gupta
2021-08-04 19:15 ` [PATCH 11/11] ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants Vineet Gupta
2021-08-05  9:02 ` [PATCH 00/11] ARC atomics update Peter Zijlstra
2021-08-05 16:18   ` Vineet Gupta
2021-08-05 17:04     ` Peter Zijlstra
2021-08-05 19:14       ` [RFC] bitops/non-atomic: make @nr unsigned to avoid any DIV Vineet Gupta
2021-08-06 13:42         ` Will Deacon
2021-08-06 19:02           ` Vineet Gupta [this message]
2021-08-06  8:41       ` [PATCH 00/11] ARC atomics update Will Deacon

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