From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032584AbdAEGGU (ORCPT ); Thu, 5 Jan 2017 01:06:20 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:48207 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032408AbdAEGEu (ORCPT ); Thu, 5 Jan 2017 01:04:50 -0500 X-AuditID: b6c32a4a-f79156d000004b6b-fb-586de1fe05a3 Subject: Re: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding To: Alim Akhtar , Jaehoon Chung , linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, cpgs@samsung.com From: "pankaj.dubey" Message-id: Date: Thu, 05 Jan 2017 11:36:32 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-version: 1.0 In-reply-to: <4110cfa2-bbe8-337e-5f2c-13d82cd23713@samsung.com> Content-type: text/plain; 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>> usbdrdphy1 = &usb3_phy1; >> }; >> + >> +Samsung Exynos SoC series PCIe PHY controller >> +-------------------------------------------------- >> +Required properties: >> +- compatible : Should be set to "samsung,exynos5440-pcie-phy" >> +- #phy-cells : Must be zero >> +- reg : a register used by phy driver. >> + - First is for phy register, second is for block register. >> +- reg-names : Must be set to "phy" and "block". >> + > In general PHY uses a "reference clock" to work, if that is true for > 5440 also, will you consider adding an (may be) optional clock > properties as well? > Yes, right, second clock, referred as "bus_clk" in pcie node should actually refer to "phy" clock. From Exynos5433 DT patch also you are mapping it to CLK_PCLK_PCIE_PHY which is a phy clk. This is same in Exynos7 as well. So better we have clocks property defined in pcie-phy binding. What do you say? >>From Exynos5440 UM, PCIe-Phy needs 250 MHz, clock and second clock used as "bus_clk" is providing 250 MHz, so this can be moved in phy driver. Thanks, Pankaj Dubey