From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D7A4C48BE5 for ; Wed, 23 Jun 2021 17:51:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB46761003 for ; Wed, 23 Jun 2021 17:51:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229889AbhFWRxU (ORCPT ); Wed, 23 Jun 2021 13:53:20 -0400 Received: from mga03.intel.com ([134.134.136.65]:4750 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbhFWRxT (ORCPT ); Wed, 23 Jun 2021 13:53:19 -0400 IronPort-SDR: 64YC395H+5wg85FOBN0TnevsXlk9+a2FiXIfogaTTuvu8REwhR+TaFcfK721JywNxdt7VvV34R 2qJcVZuxqPxA== X-IronPort-AV: E=McAfee;i="6200,9189,10024"; a="207357772" X-IronPort-AV: E=Sophos;i="5.83,294,1616482800"; d="scan'208";a="207357772" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2021 10:51:00 -0700 IronPort-SDR: 34pEdGAnHf/ASv1bGqQhp0YqQXE+yVL2/C0acUcuiCniCTsBsk+KU4s4yqHh7h2qHmwkNVU47L /4Q50Un6DXYg== X-IronPort-AV: E=Sophos;i="5.83,294,1616482800"; d="scan'208";a="487410616" Received: from eagelaga-mobl.amr.corp.intel.com (HELO [10.209.43.81]) ([10.209.43.81]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2021 10:50:58 -0700 Subject: Re: [PATCH RFC 2/7] kvm: x86: Introduce XFD MSRs as passthrough to guest To: Sean Christopherson , Jing Liu Cc: pbonzini@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, jing2.liu@intel.com References: <20210207154256.52850-1-jing2.liu@linux.intel.com> <20210207154256.52850-3-jing2.liu@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/24/21 2:43 PM, Sean Christopherson wrote: > On Sun, Feb 07, 2021, Jing Liu wrote: >> Passthrough both MSRs to let guest access and write without vmexit. > Why? Except for read-only MSRs, e.g. MSR_CORE_C1_RES, passthrough MSRs are > costly to support because KVM must context switch the MSR (which, by the by, is > completely missing from the patch). > > In other words, if these MSRs are full RW passthrough, guests with XFD enabled > will need to load the guest value on entry, save the guest value on exit, and > load the host value on exit. That's in the neighborhood of a 40% increase in > latency for a single VM-Enter/VM-Exit roundtrip (~1500 cycles => >2000 cycles). I'm not taking a position as to whether these _should_ be passthrough or not. But, if they are, I don't think you strictly need to do the RDMSR/WRMSR at VM-Exit time. Just like the "FPU", XFD isn't be used in normal kernel code. This is why we can be lazy about FPU state with TIF_NEED_FPU_LOAD. I _suspect_ that some XFD manipulation can be at least deferred to the same place where the FPU state is manipulated: places like switch_fpu_return() or kernel_fpu_begin(). Doing that would at least help the fast VM-Exit/VM-Enter paths that really like TIF_NEED_FPU_LOAD today. I guess the nasty part is that you actually need to stash the old XFD MSR value in the vcpu structure and that's not available at context-switch time. So, maybe this would only allow deferring the WRMSR. That's better than nothing I guess.