From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751843AbeCVQmW (ORCPT ); Thu, 22 Mar 2018 12:42:22 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40082 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751291AbeCVQmU (ORCPT ); Thu, 22 Mar 2018 12:42:20 -0400 Subject: Re: [PATCH v4 22/22] arm64: Add work around for Arm Cortex-A55 Erratum 1024718 To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, ckadabi@codeaurora.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, jnair@caviumnetworks.com, robin.murphy@arm.com, shankerd@codeaurora.org References: <20180313115120.17256-1-suzuki.poulose@arm.com> <20180313115120.17256-23-suzuki.poulose@arm.com> <20180321153118.GE16308@e103592.cambridge.arm.com> From: Suzuki K Poulose Message-ID: Date: Thu, 22 Mar 2018 16:42:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180321153118.GE16308@e103592.cambridge.arm.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/03/18 15:31, Dave Martin wrote: > On Tue, Mar 13, 2018 at 11:51:20AM +0000, Suzuki K Poulose wrote: >> Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer >> from an erratum 1024718, which causes incorrect updates when DBM/AP >> bits in a page table entry is modified without a break-before-make >> sequence. The work around is to skip enabling the hardware DBM feature >> on the affected cores. The hardware Access Flag management features >> is not affected. There are some other cores suffering from this >> errata, which could be added to the midr_list to trigger the work >> around. >> >> Cc: Catalin Marinas >> Cc: ckadabi@codeaurora.org >> Cc: Dave Martin >> Signed-off-by: Suzuki K Poulose > > [...] > >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 4e73c610a409..0fc097e2b72e 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -963,9 +963,23 @@ static inline void __cpu_enable_hw_dbm(void) >> isb(); >> } >> >> +static bool cpu_has_broken_dbm(void) >> +{ >> + /* List of CPUs which have broken DBM support. */ >> + static const struct midr_range cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_1024718 >> + MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 >> +#endif >> + {}, >> + }; >> + >> + return is_midr_in_range_list(read_cpuid_id(), cpus); >> +} >> + >> static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) >> { >> - return has_cpuid_feature(cap, SCOPE_LOCAL_CPU); >> + return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && >> + !cpu_has_broken_dbm(); > > This refactoring seems sensbile to me. The mapping between erratum IDs > and features that don't work is never guaranteed to be 1:1, so it > makes sense for the check function to have a generic name and to paste > in the relevant erratum ID ranges depending on the kernel config. > Thanks Dave. Apologies for the lost change log for the patch. It looked like this (before it was lost in a rebase :-() Changes since v3: - Renamed cpu_has_erratum_1024718() to cpu_has_broken_dbm() to allow for different CPU Errata configs to share a single routine for black listing CPUs. Dropped Dave's Reviewed-by > [...] > > Reviewed-by: Dave Martin Cheers Suzuki