Re: [PATCH v1 04/17] soc: tegra: Add Tegra PMC clock registrations into PMC driver

[Sowjanya Komatineni <skomatineni@nvidia.com>]

On 11/19/19 11:33 AM, Dmitry Osipenko wrote:
> 19.11.2019 09:50, Sowjanya Komatineni пишет:
>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with mux and gate for
>> each of these clocks.
>>
>> Currently these PMC clocks are registered by Tegra clock driver using
>> clk_register_mux and clk_register_gate by passing PMC base address
>> and register offsets and PMC programming for these clocks happens
>> through direct PMC access by the clock driver.
>>
>> With this, when PMC is in secure mode any direct PMC access from the
>> non-secure world does not go through and these clocks will not be
>> functional.
>>
>> This patch adds these clocks registration with PMC as a clock provider
>> for these clocks. clk_ops callback implementations for these clocks
>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming
>> in secure mode and non-secure mode.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>   drivers/soc/tegra/pmc.c | 330 ++++++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 330 insertions(+)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index 7a5aab0b993b..790a6619ba32 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -13,6 +13,9 @@
>>   
>>   #include <linux/arm-smccc.h>
>>   #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk/clk-conf.h>
>>   #include <linux/clk/tegra.h>
>>   #include <linux/debugfs.h>
>>   #include <linux/delay.h>
>> @@ -48,6 +51,7 @@
>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>> +#include <dt-bindings/soc/tegra-pmc.h>
>>   
>>   #define PMC_CNTRL			0x0
>>   #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>> @@ -108,6 +112,7 @@
>>   #define PMC_WAKE2_STATUS		0x168
>>   #define PMC_SW_WAKE2_STATUS		0x16c
>>   
>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>   #define PMC_SATA_PWRGT			0x1ac
>>   #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
>>   #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
>> @@ -170,6 +175,78 @@
>>   #define  TEGRA_SMC_PMC_READ	0xaa
>>   #define  TEGRA_SMC_PMC_WRITE	0xbb
>>   
>> +struct pmc_clk_mux {
>> +	struct clk_hw	hw;
>> +	unsigned long	offs;
>> +	u32		mask;
>> +	u32		shift;
>> +	/* register lock */
>> +	spinlock_t	*lock;
>> +};
>> +
>> +#define to_pmc_clk_mux(_hw) container_of(_hw, struct pmc_clk_mux, hw)
>> +
>> +struct pmc_clk_gate {
>> +	struct clk_hw	hw;
>> +	unsigned long	offs;
>> +	u32		shift;
>> +	/* register lock */
>> +	spinlock_t	*lock;
>> +};
>> +
>> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
>> +
>> +struct pmc_clk_init_data {
>> +	char *mux_name;
>> +	char *gate_name;
>> +	const char **parents;
>> +	int num_parents;
>> +	int mux_id;
>> +	int gate_id;
>> +	char *dev_name;
>> +	u8 mux_shift;
>> +	u8 gate_shift;
>> +	u8 init_parent;
>> +	int init_state;
>> +	struct pmc_clk_mux mux;
>> +	struct pmc_clk_gate gate;
>> +};
>> +
>> +#define PMC_CLK(_num, _mux_shift, _gate_shift, _init_parent, _init_state)\
>> +	{\
>> +		.mux_name = "clk_out_" #_num "_mux",\
>> +		.gate_name = "clk_out_" #_num,\
>> +		.parents = clk_out ##_num ##_parents,\
>> +		.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
>> +		.mux_id = TEGRA_PMC_CLK_OUT_ ##_num ##_MUX,\
>> +		.gate_id = TEGRA_PMC_CLK_OUT_ ##_num,\
>> +		.dev_name = "extern" #_num,\
>> +		.mux_shift = _mux_shift,\
>> +		.gate_shift = _gate_shift,\
>> +		.init_parent = _init_parent,\
>> +		.init_state = _init_state,\
>> +	}
>> +
>> +static DEFINE_SPINLOCK(clk_out_lock);
>> +
>> +static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern1",
>> +};
>> +
>> +static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern2",
>> +};
>> +
>> +static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
>> +	"clk_m_div4", "extern3",
>> +};
> Why these are unused?
They are used in PMC_CLK macro
>
>> +static struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>> +	PMC_CLK(1, 6, 2, 3, 1),
>> +	PMC_CLK(2, 14, 10, 0, 0),
>> +	PMC_CLK(3, 22, 18, 0, 0),
>> +};
>> +
>>   struct tegra_powergate {
>>   	struct generic_pm_domain genpd;
>>   	struct tegra_pmc *pmc;
>> @@ -279,6 +356,9 @@ struct tegra_pmc_soc {
>>   	 */
>>   	const struct tegra_wake_event *wake_events;
>>   	unsigned int num_wake_events;
>> +
>> +	struct pmc_clk_init_data *pmc_clks_data;
>> +	unsigned int num_pmc_clks;
>>   };
>>   
>>   static const char * const tegra186_reset_sources[] = {
>> @@ -2299,6 +2379,241 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>   	return NOTIFY_OK;
>>   }
>>   
>> +static void pmc_clk_fence_udelay(u32 offset)
>> +{
>> +	tegra_pmc_readl(pmc, offset);
>> +	/* pmc clk propagation delay 2 us */
>> +	udelay(2);
>> +}
>> +
>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>> +	int num_parents = clk_hw_get_num_parents(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, mux->offs) >> mux->shift;
>> +	val &= mux->mask;
>> +
>> +	if (val >= num_parents)
>> +		return -EINVAL;
>> +
>> +	return val;
>> +}
>> +
>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	struct pmc_clk_mux *mux = to_pmc_clk_mux(hw);
>> +	u32 val;
>> +	unsigned long flags = 0;
>> +
>> +	spin_lock_irqsave(mux->lock, flags);
>> +
>> +	val = tegra_pmc_readl(pmc, mux->offs);
>> +	val &= ~(mux->mask << mux->shift);
>> +	val |= index << mux->shift;
>> +	tegra_pmc_writel(pmc, val, mux->offs);
>> +	pmc_clk_fence_udelay(mux->offs);
>> +
>> +	spin_unlock_irqrestore(mux->lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct clk_ops pmc_clk_mux_ops = {
>> +	.get_parent = pmc_clk_mux_get_parent,
>> +	.set_parent = pmc_clk_mux_set_parent,
>> +	.determine_rate = __clk_mux_determine_rate,
>> +};
>> +
>> +static struct clk *
>> +tegra_pmc_clk_mux_register(const char *name, const char * const *parent_names,
>> +			   int num_parents, unsigned long flags,
>> +			   struct pmc_clk_mux *mux, unsigned long offset,
>> +			   u32 shift, u32 mask, spinlock_t *lock)
>> +{
>> +	struct clk_init_data init;
>> +
>> +	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>> +	if (!mux)
>> +		return ERR_PTR(-ENOMEM);
>> +
>> +	init.name = name;
>> +	init.ops = &pmc_clk_mux_ops;
>> +	init.parent_names = parent_names;
>> +	init.num_parents = num_parents;
>> +	init.flags = flags;
>> +
>> +	mux->hw.init = &init;
>> +	mux->offs = offset;
>> +	mux->mask = mask;
>> +	mux->shift = shift;
>> +	mux->lock = lock;
>> +
>> +	return clk_register(NULL, &mux->hw);
>> +}
>> +
>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>> +
>> +	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
>> +}
>> +
>> +static void pmc_clk_set_state(struct clk_hw *hw, int state)
>> +{
>> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
>> +	u32 val;
>> +	unsigned long flags = 0;
>> +
>> +	spin_lock_irqsave(gate->lock, flags);
>> +
>> +	val = tegra_pmc_readl(pmc, gate->offs);
>> +	val = state ? (val | BIT(gate->shift)) : (val & ~BIT(gate->shift));
>> +	tegra_pmc_writel(pmc, val, gate->offs);
>> +	pmc_clk_fence_udelay(gate->offs);
>> +
>> +	spin_unlock_irqrestore(gate->lock, flags);
>> +}
>> +
>> +static int pmc_clk_enable(struct clk_hw *hw)
>> +{
>> +	pmc_clk_set_state(hw, 1);
>> +
>> +	return 0;
>> +}
>> +
>> +static void pmc_clk_disable(struct clk_hw *hw)
>> +{
>> +	pmc_clk_set_state(hw, 0);
>> +}
>> +
>> +static const struct clk_ops pmc_clk_gate_ops = {
>> +	.is_enabled = pmc_clk_is_enabled,
>> +	.enable = pmc_clk_enable,
>> +	.disable = pmc_clk_disable,
>> +};
>> +
>> +static struct clk *
>> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
>> +			    unsigned long flags, struct pmc_clk_gate *gate,
>> +			    unsigned long offset, u32 shift, spinlock_t *lock)
>> +{
>> +	struct clk_init_data init;
>> +
>> +	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
>> +	if (!gate)
>> +		return ERR_PTR(-ENOMEM);
> Why *gate is a function argument?
for storing corresponding gate register info to use for gate clk_ops
>
>> +
>> +	init.name = name;
>> +	init.ops = &pmc_clk_gate_ops;
>> +	init.parent_names = &parent_name;
>> +	init.num_parents = 1;
>> +	init.flags = flags;
>> +
>> +	gate->hw.init = &init;
>> +	gate->offs = offset;
>> +	gate->shift = shift;
>> +	gate->lock = lock;
>> +
>> +	return clk_register(NULL, &gate->hw);
>> +}
> [snip]