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smtp.gmail.com with ESMTPSA id s6sm5518879eda.90.2019.03.12.05.22.07 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Tue, 12 Mar 2019 05:22:08 -0700 (PDT) Subject: Re: [PATCH v8 2/2] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile To: Erin Lo , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd Cc: devicetree@vger.kernel.org, srv_heupstream , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, yingjoe.chen@mediatek.com, mars.cheng@mediatek.com, eddie.huang@mediatek.com, linux-clk@vger.kernel.org, zhiyong.tao@mediatek.com, Mengqi.Zhang@mediatek.com, Ben Ho , Seiya Wang , Weiyi Lu , Hsin-Hsiung Wang References: <1552294472-32929-1-git-send-email-erin.lo@mediatek.com> <1552294472-32929-3-git-send-email-erin.lo@mediatek.com> From: Matthias Brugger Openpgp: preference=signencrypt Autocrypt: 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AN5hxlbNvNb9V2Zo5bFZjPWPFTxOteM0omUAS+QopwU0yPLLGJVf2iCmItHcUXI+r2JwH1CJ jrHWeQEI2ucSKsNa8FllDmG/fQ== Message-ID: Date: Tue, 12 Mar 2019 13:22:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <1552294472-32929-3-git-send-email-erin.lo@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/03/2019 09:54, Erin Lo wrote: > From: Ben Ho > > Add basic chip support for Mediatek 8183, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Ben Ho > Signed-off-by: Erin Lo > Signed-off-by: Seiya Wang > Signed-off-by: Weiyi Lu > Signed-off-by: Zhiyong Tao > Signed-off-by: Hsin-Hsiung Wang > Signed-off-by: Eddie Huang > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 335 ++++++++++++++++++++++++++++ > 3 files changed, 367 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index e8f952f..458bbc4 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > new file mode 100644 > index 0000000..9b52559 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +/dts-v1/; > +#include "mt8183.dtsi" > + > +/ { > + model = "MediaTek MT8183 evaluation board"; > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x80000000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > new file mode 100644 > index 0000000..64f8bd6 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -0,0 +1,335 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8183"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + }; > + > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + pmu-a73 { > + compatible = "arm,cortex-a73-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = ; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > + }; > + }; > + }; > + > + mcucfg: syscon@c530000 { > + compatible = "mediatek,mt8183-mcucfg", "syscon"; Binding is not documented. I found some other bindings not documented as well. Please update the binding documentation to add this compatible, otherwise I won't be able to take this patch. Regards, Matthias > + reg = <0 0x0c530000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@c530a80 { > + compatible = "mediatek,mt8183-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c530a80 0 0x50>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8183-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8183-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + #interrupt-cells = <3>; > + }; > + > + apmixedsys: syscon@1000c000 { > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pwrap: pwrap@1000d000 { > + compatible = "mediatek,mt8183-pwrap"; > + reg = <0 0x1000d000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > + <&infracfg CLK_INFRA_PMIC_AP>; > + clock-names = "spi", "wrap"; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audiosys: syscon@11220000 { > + compatible = "mediatek,mt8183-audiosys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: syscon@13000000 { > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt8183-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt8183-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: syscon@16000000 { > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: syscon@17000000 { > + compatible = "mediatek,mt8183-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_conn: syscon@19000000 { > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_adl: syscon@19010000 { > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > + reg = <0 0x19010000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core0: syscon@19180000 { > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > + reg = <0 0x19180000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core1: syscon@19280000 { > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > + reg = <0 0x19280000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt8183-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > +}; >