From: Maxime Ripard <maxime@cerno.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Eric Anholt <eric@anholt.net>
Cc: dri-devel@lists.freedesktop.org,
linux-rpi-kernel@lists.infradead.org,
bcm-kernel-feedback-list@broadcom.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
Tim Gover <tim.gover@raspberrypi.com>,
Phil Elwell <phil@raspberrypi.com>,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v2 52/91] drm/vc4: crtc: Assign output to channel automatically
Date: Fri, 24 Apr 2020 17:34:33 +0200 [thread overview]
Message-ID: <d82fb3d34a7606e92050ca460e4be9ca0c5ffdb6.1587742492.git-series.maxime@cerno.tech> (raw)
In-Reply-To: <cover.d1e741d37e43e1ba2d2ecd93fc81d42a6df99d14.1587742492.git-series.maxime@cerno.tech>
The HVS found in the BCM2711 has 6 outputs and 3 FIFOs, with each output
being connected to a pixelvalve, and some muxing between the FIFOs and
outputs.
Any output cannot feed from any FIFO though, and they all have a bunch of
constraints.
In order to support this, let's store the possible FIFOs each output can be
assigned to in the vc4_crtc_data, and use that information at atomic_check
time to iterate over all the CRTCs enabled and assign them FIFOs.
The channel assigned is then set in the vc4_crtc_state so that the rest of
the driver can use it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 37 +++++----
drivers/gpu/drm/vc4/vc4_drv.h | 7 +-
drivers/gpu/drm/vc4/vc4_kms.c | 142 ++++++++++++++++++++++++++++++++--
drivers/gpu/drm/vc4/vc4_regs.h | 10 ++-
4 files changed, 172 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 00e6ecf5a6d4..ea55d4ca2766 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -91,6 +91,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
unsigned int cob_size;
u32 val;
int fifo_lines;
@@ -107,7 +108,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
* Read vertical scanline which is currently composed for our
* pixelvalve by the HVS, and also the scaler status.
*/
- val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
+ val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
/* Get optional system timestamp after query. */
if (etime)
@@ -127,7 +128,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
*hpos += mode->crtc_htotal / 2;
}
- cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc->channel);
+ cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc_state->assigned_channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
fifo_lines = cob_size / mode->crtc_hdisplay;
@@ -214,6 +215,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
u32 i;
/* The LUT memory is laid out with each HVS channel in order,
@@ -222,7 +224,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
*/
HVS_WRITE(SCALER_GAMADDR,
SCALER_GAMADDR_AUTOINC |
- (vc4_crtc->channel * 3 * crtc->gamma_size));
+ (vc4_crtc_state->assigned_channel * 3 * crtc->gamma_size));
for (i = 0; i < crtc->gamma_size; i++)
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
@@ -394,7 +396,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_print_regset32(&p, &vc4_crtc->regset);
}
- if (vc4_crtc->channel == 2) {
+ if (vc4_crtc->data->hvs_output == 2) {
u32 dispctrl;
u32 dsp3_mux;
@@ -421,7 +423,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (!vc4_state->feed_txp)
vc4_crtc_config_pv(crtc);
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
SCALER_DISPBKGND_AUTOHS |
SCALER_DISPBKGND_GAMMA |
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
@@ -453,7 +455,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- u32 chan = vc4_crtc->channel;
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(old_state);
+ u32 chan = vc4_crtc_state->assigned_channel;
int ret;
require_hvs_enabled(dev);
@@ -532,12 +535,12 @@ static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
crtc->state->event = NULL;
}
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
spin_unlock_irqrestore(&dev->event_lock, flags);
} else {
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
}
}
@@ -586,7 +589,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
(vc4_state->feed_txp ?
SCALER5_DISPCTRLX_ONESHOT : 0);
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_state->assigned_channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
@@ -702,7 +705,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_plane *plane;
struct vc4_plane_state *vc4_plane_state;
@@ -744,8 +746,8 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
/* This sets a black background color fill, as is the case
* with other DRM drivers.
*/
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
- HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
+ HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
SCALER_DISPBKGND_FILL);
/* Only update DISPLIST if the CRTC was already running and is not
@@ -759,7 +761,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
vc4_crtc_update_dlist(crtc);
if (crtc->state->color_mgmt_changed) {
- u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
+ u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
if (crtc->state->gamma_lut) {
vc4_crtc_update_gamma_lut(crtc);
@@ -771,7 +773,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
*/
dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
}
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
}
if (debug_dump_regs) {
@@ -802,7 +804,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- u32 chan = vc4_crtc->channel;
+ u32 chan = vc4_state->assigned_channel;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
@@ -1001,6 +1003,7 @@ static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
old_vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state->feed_txp = old_vc4_state->feed_txp;
vc4_state->margins = old_vc4_state->margins;
+ vc4_state->assigned_channel = old_vc4_state->assigned_channel;
__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
return &vc4_state->base;
@@ -1062,6 +1065,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
};
static const struct vc4_crtc_data bcm2835_pv0_data = {
+ .hvs_available_channels = BIT(0),
.hvs_output = 0,
.debugfs_name = "crtc0_regs",
.pixels_per_clock = 1,
@@ -1072,6 +1076,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = {
};
static const struct vc4_crtc_data bcm2835_pv1_data = {
+ .hvs_available_channels = BIT(2),
.hvs_output = 2,
.debugfs_name = "crtc1_regs",
.pixels_per_clock = 1,
@@ -1082,6 +1087,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = {
};
static const struct vc4_crtc_data bcm2835_pv2_data = {
+ .hvs_available_channels = BIT(1),
.hvs_output = 1,
.debugfs_name = "crtc2_regs",
.pixels_per_clock = 1,
@@ -1173,7 +1179,6 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
&vc4_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 6fe36a38a8b3..6468c6df20b6 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -450,6 +450,9 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
+ /* Which channels of the HVS can the output source from */
+ unsigned int hvs_available_channels;
+
/* Which output of the HVS this pixelvalve sources from. */
int hvs_output;
@@ -469,9 +472,6 @@ struct vc4_crtc {
/* Timestamp at start of vblank irq - unaffected by lock delays. */
ktime_t t_vblank;
- /* Which HVS channel we're using for our CRTC. */
- int channel;
-
u8 lut_r[256];
u8 lut_g[256];
u8 lut_b[256];
@@ -493,6 +493,7 @@ struct vc4_crtc_state {
struct drm_mm_node mm;
bool feed_txp;
bool txp_armed;
+ unsigned int assigned_channel;
struct {
unsigned int left;
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 851f0740b260..06afffe1c22b 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -11,6 +11,8 @@
* crtc, HDMI encoder).
*/
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <drm/drm_atomic.h>
@@ -146,6 +148,72 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
}
+static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ unsigned char dsp2_mux = 0;
+ unsigned char dsp3_mux = 3;
+ unsigned char dsp4_mux = 3;
+ unsigned char dsp5_mux = 3;
+ unsigned int i;
+ u32 reg;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+ if (!crtc_state->active)
+ continue;
+
+ switch (vc4_crtc->data->hvs_output) {
+ case 2:
+ dsp2_mux = (vc4_state->assigned_channel == 2) ? 1 : 0;
+ break;
+
+ case 3:
+ dsp3_mux = vc4_state->assigned_channel;
+ break;
+
+ case 4:
+ dsp4_mux = vc4_state->assigned_channel;
+ break;
+
+ case 5:
+ dsp5_mux = vc4_state->assigned_channel;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ reg = HVS_READ(SCALER_DISPECTRL);
+ if (FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg) != dsp2_mux)
+ HVS_WRITE(SCALER_DISPECTRL,
+ (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
+ VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
+
+ reg = HVS_READ(SCALER_DISPCTRL);
+ if (FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg) != dsp3_mux)
+ HVS_WRITE(SCALER_DISPCTRL,
+ (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
+ VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
+
+ reg = HVS_READ(SCALER_DISPEOLN);
+ if (FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg) != dsp4_mux)
+ HVS_WRITE(SCALER_DISPEOLN,
+ (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
+ VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
+
+ reg = HVS_READ(SCALER_DISPDITHER);
+ if (FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg) != dsp5_mux)
+ HVS_WRITE(SCALER_DISPDITHER,
+ (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
+ VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
+}
+
static void
vc4_atomic_complete_commit(struct drm_atomic_state *state)
{
@@ -156,11 +224,15 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
int i;
for (i = 0; i < dev->mode_config.num_crtc; i++) {
- if (!state->crtcs[i].ptr || !state->crtcs[i].commit)
+ struct __drm_crtcs_state *_state = &state->crtcs[i];
+ struct vc4_crtc_state *vc4_crtc_state;
+
+ if (!_state->ptr || !_state->commit)
continue;
- vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr);
- vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
+ vc4_crtc = to_vc4_crtc(_state->ptr);
+ vc4_crtc_state = to_vc4_crtc_state(_state->state);
+ vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
}
clk_set_rate(hvs->core_clk, 500000000);
@@ -172,6 +244,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
drm_atomic_helper_commit_modeset_disables(dev, state);
vc4_ctm_commit(vc4, state);
+ vc4_hvs_pv_muxing_commit(vc4, state);
drm_atomic_helper_commit_planes(dev, state, 0);
@@ -381,8 +454,11 @@ vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
/* CTM is being enabled or the matrix changed. */
if (new_crtc_state->ctm) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(new_crtc_state);
+
/* fifo is 1-based since 0 disables CTM. */
- int fifo = to_vc4_crtc(crtc)->channel + 1;
+ int fifo = vc4_crtc_state->assigned_channel + 1;
/* Check userland isn't trying to turn on CTM for more
* than one CRTC at a time.
@@ -495,10 +571,66 @@ static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
.atomic_destroy_state = vc4_load_tracker_destroy_state,
};
+#define NUM_OUTPUTS 6
+#define NUM_CHANNELS 3
+
static int
vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
{
- int ret;
+ unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ int i, ret;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ bool is_assigned = false;
+ unsigned int channel;
+
+ if (!crtc_state->active)
+ continue;
+
+ /*
+ * The problem we have to solve here is that we have
+ * up to 7 encoders, connected to up to 6 CRTCs.
+ *
+ * Those CRTCs, depending on the instance, can be
+ * routed to 1, 2 or 3 HVS FIFOs, and we need to set
+ * the change the muxing between FIFOs and outputs in
+ * the HVS accordingly.
+ *
+ * It would be pretty hard to come up with an
+ * algorithm that would generically solve
+ * this. However, the current routing trees we support
+ * allow us to simplify a bit the problem.
+ *
+ * Indeed, with the current supported layouts, if we
+ * try to assign in the ascending crtc index order the
+ * FIFOs, we can't fall into the situation where an
+ * earlier CRTC that had multiple routes is assigned
+ * one that was the only option for a later CRTC.
+ *
+ * If the layout changes and doesn't give us that in
+ * the future, we will need to have something smarter,
+ * but it works so far.
+ */
+ for_each_set_bit(channel, &unassigned_channels,
+ sizeof(unassigned_channels)) {
+
+ if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
+ continue;
+
+ vc4_crtc_state->assigned_channel = channel;
+ unassigned_channels &= ~BIT(channel);
+ is_assigned = true;
+ break;
+ }
+
+ if (!is_assigned)
+ return -EINVAL;
+ }
ret = vc4_ctm_atomic_check(dev, state);
if (ret < 0)
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 8a51baf681fe..b96ebbb1354b 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -287,9 +287,19 @@
#define SCALER_DISPID 0x00000008
#define SCALER_DISPECTRL 0x0000000c
+# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
+# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
+
#define SCALER_DISPPROF 0x00000010
+
#define SCALER_DISPDITHER 0x00000014
+# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
+# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPEOLN 0x00000018
+# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
+# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPLIST0 0x00000020
#define SCALER_DISPLIST1 0x00000024
#define SCALER_DISPLIST2 0x00000028
--
git-series 0.9.1
next prev parent reply other threads:[~2020-04-24 15:36 UTC|newest]
Thread overview: 142+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 15:33 [PATCH v2 00/91] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 01/91] i2c: brcmstb: Allow to compile it on BCM2835 Maxime Ripard
2020-04-24 16:13 ` Wolfram Sang
2020-04-24 17:07 ` Florian Fainelli
2020-04-24 19:04 ` Wolfram Sang
2020-04-26 7:44 ` Wolfram Sang
2020-04-24 15:33 ` [PATCH v2 02/91] dt-bindings: arm: bcm: Convert BCM2835 firmware binding to YAML Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 03/91] dt-bindings: clock: Add a binding for the RPi Firmware clocks Maxime Ripard
2020-05-11 21:47 ` Rob Herring
2020-05-13 8:13 ` Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 04/91] firmware: rpi: Only create clocks device if we don't have a node for it Maxime Ripard
2020-04-27 11:24 ` Nicolas Saenz Julienne
2020-04-28 13:50 ` Maxime Ripard
2020-04-30 16:27 ` Nicolas Saenz Julienne
2020-04-24 15:33 ` [PATCH v2 05/91] clk: bcm: rpi: Allow the driver to be probed by DT Maxime Ripard
2020-04-30 16:19 ` Nicolas Saenz Julienne
2020-04-24 15:33 ` [PATCH v2 06/91] clk: bcm: rpi: Statically init clk_init_data Maxime Ripard
2020-05-27 6:47 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 07/91] clk: bcm: rpi: Use clk_hw_register for pllb_arm Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 08/91] clk: bcm: rpi: Remove global pllb_arm clock pointer Maxime Ripard
2020-05-27 6:48 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 09/91] clk: bcm: rpi: Make sure pllb_arm is removed Maxime Ripard
2020-05-27 6:48 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 10/91] clk: bcm: rpi: Remove pllb_arm_lookup global pointer Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 11/91] clk: bcm: rpi: Switch to clk_hw_register_clkdev Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 12/91] clk: bcm: rpi: Make sure the clkdev lookup is removed Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 13/91] clk: bcm: rpi: Create a data structure for the clocks Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 14/91] clk: bcm: rpi: Add clock id to data Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 15/91] clk: bcm: rpi: Pass the clocks data to the firmware function Maxime Ripard
2020-05-27 6:49 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 16/91] clk: bcm: rpi: Rename is_prepared function Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 17/91] clk: bcm: rpi: Split pllb clock hooks Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 18/91] clk: bcm: rpi: Make the PLLB registration function return a clk_hw Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 19/91] clk: bcm: rpi: Add DT provider for the clocks Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 20/91] clk: bcm: rpi: Discover the firmware clocks Maxime Ripard
2020-05-04 12:05 ` Nicolas Saenz Julienne
2020-05-15 8:19 ` Maxime Ripard
2020-05-21 9:13 ` Nicolas Saenz Julienne
2020-05-27 7:03 ` Stephen Boyd
2020-04-24 15:34 ` [PATCH v2 21/91] ARM: dts: bcm2711: Add firmware clocks node Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 22/91] reset: Move reset-simple header out of drivers/reset Maxime Ripard
2020-05-06 9:26 ` Philipp Zabel
2020-05-13 11:52 ` Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 23/91] reset: simple: Add reset callback Maxime Ripard
2020-05-06 9:26 ` Philipp Zabel
2020-04-24 15:34 ` [PATCH v2 24/91] dt-bindings: clock: Add BCM2711 DVP binding Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 25/91] clk: bcm: Add BCM2711 DVP driver Maxime Ripard
2020-05-27 7:06 ` Stephen Boyd
2020-04-24 15:34 ` [PATCH v2 26/91] ARM: dts: bcm2711: Add HDMI DVP Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 27/91] dt-bindings: display: Convert VC4 bindings to schemas Maxime Ripard
2020-04-27 21:32 ` Rob Herring
2020-04-24 15:34 ` [PATCH v2 28/91] dt-bindings: display: vc4: dpi: Add missing clock-names property Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 29/91] dt-bindings: display: vc4: dsi: Add missing clock properties Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 30/91] dt-bindings: display: vc4: hdmi: Add missing clock-names property Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 31/91] dt-bindings: display: vc4: Document BCM2711 VC5 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 32/91] drm/vc4: drv: Add include guards Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 33/91] drm/vc4: drv: Support BCM2711 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 34/91] dt-bindings: display: Add support for the BCM2711 HVS Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 35/91] drm/vc4: Add support for the BCM2711 HVS5 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 36/91] drm/vc4: hvs: Boost the core clock during modeset Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 37/91] drm/vc4: plane: Improve LBM usage Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 38/91] drm/vc4: plane: Move planes creation to its own function Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 39/91] drm/vc4: plane: Move additional planes creation to driver Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 40/91] drm/vc4: plane: Register all the planes at once Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 41/91] drm/vc4: plane: Create overlays for any CRTC Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 42/91] drm/vc4: plane: Create more planes Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 43/91] drm/vc4: crtc: Rename SoC data structures Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 44/91] drm/vc4: crtc: Move crtc state to common header Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 45/91] drm/vc4: crtc: Deal with different number of pixel per clock Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 46/91] drm/vc4: crtc: Use a shared interrupt Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 47/91] drm/vc4: crtc: Turn static const variable into a define Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 48/91] drm/vc4: crtc: Move the cob allocation outside of bind Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 49/91] drm/vc4: crtc: Rename HVS channel to output Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 50/91] drm/vc4: crtc: Use local chan variable Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 51/91] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Maxime Ripard
2020-04-24 15:34 ` Maxime Ripard [this message]
2020-04-24 15:34 ` [PATCH v2 53/91] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 54/91] drm/vc4: crtc: Add function to compute FIFO level bits Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 55/91] drm/vc4: crtc: Rename HDMI encoder type to HDMI0 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 56/91] drm/vc4: crtc: Add HDMI1 encoder type Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 57/91] drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 58/91] drm/vc4: crtc: Disable color management for HVS5 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 59/91] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 60/91] drm/vc4: crtc: Add BCM2711 pixelvalves Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 61/91] drm/vc4: hdmi: Use debugfs private field Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 62/91] drm/vc4: hdmi: Move structure to header Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 63/91] drm/vc4: hdmi: rework connectors and encoders Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 64/91] drm/vc4: hdmi: Remove DDC argument to connector_init Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 65/91] drm/vc4: hdmi: Rename hdmi to vc4_hdmi Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 66/91] drm/vc4: hdmi: Move accessors " Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 67/91] drm/vc4: hdmi: Use local vc4_hdmi directly Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 68/91] drm/vc4: hdmi: Add container_of macros for encoders and connectors Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 69/91] drm/vc4: hdmi: Pass vc4_hdmi to CEC code Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 70/91] drm/vc4: hdmi: Remove vc4_dev hdmi pointer Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 71/91] drm/vc4: hdmi: Remove vc4_hdmi_connector Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 72/91] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard
2020-04-25 21:06 ` Stefan Wahren
2020-04-24 15:34 ` [PATCH v2 73/91] drm/vc4: hdmi: Implement a register layout abstraction Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 74/91] drm/vc4: hdmi: Add reset callback Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 75/91] drm/vc4: hdmi: Add PHY init and disable function Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 76/91] drm/vc4: hdmi: Add PHY RNG enable / " Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 77/91] drm/vc4: hdmi: Add a CSC setup callback Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 78/91] drm/vc4: hdmi: Store the encoder type in the variant structure Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 79/91] drm/vc4: hdmi: Deal with multiple debugfs files Maxime Ripard
2020-04-25 21:26 ` Stefan Wahren
2020-04-28 15:57 ` Maxime Ripard
2020-04-28 16:19 ` Dave Stevenson
2020-04-24 15:35 ` [PATCH v2 80/91] drm/vc4: hdmi: Move CEC init to its own function Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 81/91] drm/vc4: hdmi: Add CEC support flag Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 82/91] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 83/91] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 84/91] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 85/91] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 86/91] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 87/91] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 88/91] drm/vc4: hdmi: Add audio-related callbacks Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 89/91] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard
2020-05-07 17:36 ` Stefan Wahren
2020-04-24 15:35 ` [PATCH v2 90/91] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings Maxime Ripard
2020-05-11 21:50 ` Rob Herring
2020-05-13 8:16 ` Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 91/91] ARM: dts: bcm2711: Enable the display pipeline Maxime Ripard
2020-04-25 20:54 ` Stefan Wahren
2020-04-28 14:11 ` Maxime Ripard
2020-04-27 7:23 ` [PATCH v2 00/91] drm/vc4: Support BCM2711 Display Pipelin Jian-Hong Pan
2020-04-28 16:21 ` Maxime Ripard
2020-05-04 6:35 ` Jian-Hong Pan
2020-05-07 17:21 ` Maxime Ripard
2020-05-08 6:20 ` Jian-Hong Pan
2020-05-11 3:12 ` Jian-Hong Pan
2020-05-25 11:11 ` Maxime Ripard
2020-05-26 10:20 ` Maxime Ripard
2020-05-27 3:49 ` Daniel Drake
2020-05-27 9:13 ` Maxime Ripard
2020-05-27 9:15 ` Daniel Drake
2020-05-28 7:30 ` Maxime Ripard
2020-06-01 7:58 ` Jian-Hong Pan
2020-06-02 11:04 ` Maxime Ripard
2020-06-05 8:44 ` Jian-Hong Pan
2020-06-29 14:21 ` Maxime Ripard
2020-06-30 8:26 ` Jian-Hong Pan
2020-07-03 12:56 ` Maxime Ripard
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