From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support
Date: Fri, 2 Aug 2019 13:37:50 -0700 [thread overview]
Message-ID: <d8d2732f-8fde-4702-edab-67edf459ec3d@nvidia.com> (raw)
In-Reply-To: <92e95688-1984-9967-d47c-57380466a0f2@gmail.com>
On 8/2/19 1:20 PM, Dmitry Osipenko wrote:
> 02.08.2019 21:43, Sowjanya Komatineni пишет:
>> On 8/2/19 5:32 AM, Dmitry Osipenko wrote:
>>> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>>>> This patch implements save and restore context for peripheral fixed
>>>> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
>>>> peripheral clock ops.
>>>>
>>>> During system suspend, core power goes off and looses the settings
>>>> of the Tegra CAR controller registers.
>>>>
>>>> So during suspend entry clock and reset state of peripherals is saved
>>>> and on resume they are restored to have clocks back to same rate and
>>>> state as before suspend.
>>>>
>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-periph-fixed.c | 33
>>>> ++++++++++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk-periph-gate.c | 34
>>>> +++++++++++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk-periph.c | 37
>>>> ++++++++++++++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk-sdmmc-mux.c | 28 +++++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk.h | 6 ++++++
>>>> 5 files changed, 138 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-periph-fixed.c
>>>> b/drivers/clk/tegra/clk-periph-fixed.c
>>>> index c088e7a280df..21b24530fa00 100644
>>>> --- a/drivers/clk/tegra/clk-periph-fixed.c
>>>> +++ b/drivers/clk/tegra/clk-periph-fixed.c
>>>> @@ -60,11 +60,44 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw
>>>> *hw,
>>>> return (unsigned long)rate;
>>>> }
>>>> +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
>>>> +{
>>>> + struct tegra_clk_periph_fixed *fixed =
>>>> to_tegra_clk_periph_fixed(hw);
>>>> + u32 mask = 1 << (fixed->num % 32);
>>> This could be BIT(fixed->num % 32).
>>>
>>>> + fixed->enb_ctx = readl_relaxed(fixed->base +
>>>> fixed->regs->enb_reg) &
>>>> + mask;
>>>> + fixed->rst_ctx = readl_relaxed(fixed->base +
>>>> fixed->regs->rst_reg) &
>>>> + mask;
>>> The enb_ctx/rst_ctx are booleans, while you assigning an integer value
>>> here. You're getting away here because bool is an 32bit unsigned int,
>>> but you shouldn't rely on it and always explicitly convert to a bool.
>>>
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw)
>>>> +{
>>>> + struct tegra_clk_periph_fixed *fixed =
>>>> to_tegra_clk_periph_fixed(hw);
>>>> + u32 mask = 1 << (fixed->num % 32);
>>>> +
>>>> + if (fixed->enb_ctx)
>>>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_set_reg);
>>>> + else
>>>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_clr_reg);
>>>> +
>>>> + udelay(2);
>>> Will be better to read out and compare the hardware's state with the
>>> restored one, then bail out if the state is unchanged.
>>>
>>> Shouldn't it be fence_udelay()?
>>>
>>>> + if (!fixed->rst_ctx) {
>>>> + udelay(5); /* reset propogation delay */
>>> Why delaying is done before the writing to the reset register?
>> During SC7 exit, peripheral reset state is set to POR state. So some
>> peripherals will already be in reset state and making sure of
>> propagation delay before releasing from reset.
>>
>> It should be rst_clr_reg. will fix in next rev
>>
>>>> + writel_relaxed(mask, fixed->base + fixed->regs->rst_reg);
>>> I'm not quite sure what's going on here, this looks wrong.
>>>
>>> 1. rst_reg points to RST_DEVICES_x
>>> 2. Each bit of RST_DEVICES_x represents the reset-assertion state of
>>> each individual device
>>> 3. By writing to rst_reg, all (!) devices are deasserted, except the one
>>> device which corresponds to the mask
>>> 4. The reset is asserted for a single device, while !fixed->rst_ctx
>>> means that it actually should be deasserted (?)
>>>
>>> Apparently you should use rst_set_reg / rst_clr_reg.
>> Yes, It should be rst_clr_reg. will fix in next rev
>>>> + }
>>> What about the case where rst_ctx=true?
>> ON SC7 exit, state of RST_DEV will be POR state where most peripherals
>> will already be in reset state.
>>
>> Few of them which are not in reset state in POR values are those that
>> need to stay de-asserted across the boot states anyway.
> Okay, sounds reasonable.
>
> BTW, it would be nice if you could add a brief clarifying comment to the
> code for each of the questions asked during of the review.
OK, Will add comments in code ...
next prev parent reply other threads:[~2019-08-02 20:37 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 0:20 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 02/20] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-07-31 10:49 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 04/20] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 05/20] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-31 11:11 ` Dmitry Osipenko
2019-07-31 21:04 ` Sowjanya Komatineni
2019-08-01 10:53 ` Dmitry Osipenko
2019-08-01 18:06 ` Sowjanya Komatineni
2019-08-01 18:42 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-31 9:50 ` Dmitry Osipenko
2019-07-31 10:44 ` Dmitry Osipenko
2019-07-31 23:09 ` Sowjanya Komatineni
2019-08-01 17:58 ` Sowjanya Komatineni
2019-08-01 19:00 ` Dmitry Osipenko
2019-08-01 19:42 ` Sowjanya Komatineni
2019-08-01 20:17 ` Dmitry Osipenko
2019-08-01 20:31 ` Sowjanya Komatineni
2019-08-01 20:54 ` Dmitry Osipenko
2019-08-01 21:30 ` Sowjanya Komatineni
2019-08-01 23:19 ` Sowjanya Komatineni
2019-08-01 23:49 ` Sowjanya Komatineni
2019-08-02 12:38 ` Dmitry Osipenko
2019-08-02 18:33 ` Sowjanya Komatineni
2019-08-02 20:13 ` Dmitry Osipenko
2019-08-02 20:17 ` Dmitry Osipenko
2019-08-02 20:32 ` Sowjanya Komatineni
2019-08-02 21:15 ` Dmitry Osipenko
2019-08-02 21:18 ` Sowjanya Komatineni
2019-08-02 23:51 ` Sowjanya Komatineni
2019-08-03 10:33 ` Dmitry Osipenko
2019-08-03 17:01 ` Sowjanya Komatineni
2019-08-03 23:44 ` Sowjanya Komatineni
2019-08-04 12:24 ` Dmitry Osipenko
2019-08-04 12:31 ` Dmitry Osipenko
2019-08-02 12:32 ` Dmitry Osipenko
2019-08-02 18:43 ` Sowjanya Komatineni
2019-08-02 20:20 ` Dmitry Osipenko
2019-08-02 20:37 ` Sowjanya Komatineni [this message]
2019-07-31 0:20 ` [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-31 10:14 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 09/20] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-31 10:12 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 11/20] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-31 10:23 ` Dmitry Osipenko
2019-07-31 11:14 ` Dmitry Osipenko
2019-07-31 21:05 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 12/20] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 13/20] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 14/20] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 15/20] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-31 11:04 ` Dmitry Osipenko
2019-07-31 21:08 ` Sowjanya Komatineni
2019-08-01 10:43 ` Dmitry Osipenko
2019-08-01 17:56 ` Sowjanya Komatineni
2019-08-01 18:39 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 17/20] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 19/20] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 20/20] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
2019-07-31 21:10 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 21:10 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d8d2732f-8fde-4702-edab-67edf459ec3d@nvidia.com \
--to=skomatineni@nvidia.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=jason@lakedaemon.net \
--cc=jckuo@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=josephl@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=mperttunen@nvidia.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=spatra@nvidia.com \
--cc=stefan@agner.ch \
--cc=talho@nvidia.com \
--cc=tglx@linutronix.de \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).