From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753231AbdGJDHZ (ORCPT ); Sun, 9 Jul 2017 23:07:25 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:48661 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753161AbdGJDHY (ORCPT ); Sun, 9 Jul 2017 23:07:24 -0400 From: Anshuman Khandual Subject: Re: [RFC v5 38/38] Documentation: PowerPC specific updates to memory protection keys To: Ram Pai , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, x86@kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org References: <1499289735-14220-1-git-send-email-linuxram@us.ibm.com> <1499289735-14220-39-git-send-email-linuxram@us.ibm.com> Cc: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, khandual@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, bsingharora@gmail.com, dave.hansen@intel.com, hbabu@us.ibm.com, arnd@arndb.de, akpm@linux-foundation.org, corbet@lwn.net, mingo@redhat.com Date: Mon, 10 Jul 2017 08:37:04 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1499289735-14220-39-git-send-email-linuxram@us.ibm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable x-cbid: 17071003-0040-0000-0000-00000342E4FD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17071003-0041-0000-0000-00000CBE32B9 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-10_01:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1707100053 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/06/2017 02:52 AM, Ram Pai wrote: > Add documentation updates that capture PowerPC specific changes. > > Signed-off-by: Ram Pai > --- > Documentation/vm/protection-keys.txt | 85 ++++++++++++++++++++++++++-------- > 1 files changed, 65 insertions(+), 20 deletions(-) > > diff --git a/Documentation/vm/protection-keys.txt b/Documentation/vm/protection-keys.txt > index b643045..d50b6ab 100644 > --- a/Documentation/vm/protection-keys.txt > +++ b/Documentation/vm/protection-keys.txt > @@ -1,21 +1,46 @@ > -Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature > -which will be found on future Intel CPUs. > +Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature found in > +new generation of intel CPUs and on PowerPC 7 and higher CPUs. > > Memory Protection Keys provides a mechanism for enforcing page-based > -protections, but without requiring modification of the page tables > -when an application changes protection domains. It works by > -dedicating 4 previously ignored bits in each page table entry to a > -"protection key", giving 16 possible keys. > - > -There is also a new user-accessible register (PKRU) with two separate > -bits (Access Disable and Write Disable) for each key. Being a CPU > -register, PKRU is inherently thread-local, potentially giving each > -thread a different set of protections from every other thread. > - > -There are two new instructions (RDPKRU/WRPKRU) for reading and writing > -to the new register. The feature is only available in 64-bit mode, > -even though there is theoretically space in the PAE PTEs. These > -permissions are enforced on data access only and have no effect on > +protections, but without requiring modification of the page tables when an > +application changes protection domains. > + > + > +On Intel: > + > + It works by dedicating 4 previously ignored bits in each page table > + entry to a "protection key", giving 16 possible keys. > + > + There is also a new user-accessible register (PKRU) with two separate > + bits (Access Disable and Write Disable) for each key. Being a CPU > + register, PKRU is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. > + > + There are two new instructions (RDPKRU/WRPKRU) for reading and writing > + to the new register. The feature is only available in 64-bit mode, > + even though there is theoretically space in the PAE PTEs. These > + permissions are enforced on data access only and have no effect on > + instruction fetches. > + > + > +On PowerPC: > + > + It works by dedicating 5 page table entry bits to a "protection key", > + giving 32 possible keys. > + > + There is a user-accessible register (AMR) with two separate bits; > + Access Disable and Write Disable, for each key. Being a CPU > + register, AMR is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. NOTE: > + Disabling read permission does not disable write and vice-versa. We can only enable/disable entire access or write. Then how read permission can be changed with protection keys directly ?