From: Julien <julien.thierry.kdev@gmail.com>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>
Cc: John Garry <john.garry@huawei.com>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
Lokesh Vutla <lokeshvutla@ti.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 06/12] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts
Date: Thu, 22 Aug 2019 16:05:54 +0100 [thread overview]
Message-ID: <daa0ff03-cf73-e1de-b4b2-d1382c5d5548@gmail.com> (raw)
In-Reply-To: <20190806100121.240767-7-maz@kernel.org>
Hi Marc,
On 06/08/19 11:01, Marc Zyngier wrote:
> As we're about to have a variable number of PPIs, let's make the
> allocation of the NMI refcounts dynamic. Also apply some minor
> cleanups (moving things around).
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Julien Thierry <julien.thierry.kdev@gmail.com>
Thanks,
> ---
> drivers/irqchip/irq-gic-v3.c | 47 ++++++++++++++++++++++++++----------
> 1 file changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index e03fb6d7c2ce..4253c7f67c86 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -88,7 +88,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
> static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
>
> /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
> -static refcount_t ppi_nmi_refs[16];
> +static refcount_t *ppi_nmi_refs;
>
> static struct gic_kvm_info gic_v3_kvm_info;
> static DEFINE_PER_CPU(bool, has_rss);
> @@ -409,6 +409,16 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
> writeb_relaxed(prio, base + offset + index);
> }
>
> +static u32 gic_get_ppi_index(struct irq_data *d)
> +{
> + switch (get_intid_range(d)) {
> + case PPI_RANGE:
> + return d->hwirq - 16;
> + default:
> + unreachable();
> + }
> +}
> +
> static int gic_irq_nmi_setup(struct irq_data *d)
> {
> struct irq_desc *desc = irq_to_desc(d->irq);
> @@ -429,10 +439,12 @@ static int gic_irq_nmi_setup(struct irq_data *d)
> return -EINVAL;
>
> /* desc lock should already be held */
> - if (gic_irq(d) < 32) {
> + if (gic_irq_in_rdist(d)) {
> + u32 idx = gic_get_ppi_index(d);
> +
> /* Setting up PPI as NMI, only switch handler for first NMI */
> - if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) {
> - refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1);
> + if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
> + refcount_set(&ppi_nmi_refs[idx], 1);
> desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
> }
> } else {
> @@ -464,9 +476,11 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
> return;
>
> /* desc lock should already be held */
> - if (gic_irq(d) < 32) {
> + if (gic_irq_in_rdist(d)) {
> + u32 idx = gic_get_ppi_index(d);
> +
> /* Tearing down NMI, only switch handler for last NMI */
> - if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16]))
> + if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
> desc->handle_irq = handle_percpu_devid_irq;
> } else {
> desc->handle_irq = handle_fasteoi_irq;
> @@ -1394,7 +1408,19 @@ static void gic_enable_nmi_support(void)
> {
> int i;
>
> - for (i = 0; i < 16; i++)
> + if (!gic_prio_masking_enabled())
> + return;
> +
> + if (gic_has_group0() && !gic_dist_security_disabled()) {
> + pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
> + return;
> + }
> +
> + ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
> + if (!ppi_nmi_refs)
> + return;
> +
> + for (i = 0; i < gic_data.ppi_nr; i++)
> refcount_set(&ppi_nmi_refs[i], 0);
>
> static_branch_enable(&supports_pseudo_nmis);
> @@ -1472,12 +1498,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
> gicv2m_init(handle, gic_data.domain);
> }
>
> - if (gic_prio_masking_enabled()) {
> - if (!gic_has_group0() || gic_dist_security_disabled())
> - gic_enable_nmi_support();
> - else
> - pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
> - }
> + gic_enable_nmi_support();
>
> return 0;
>
>
--
Julien Thierry
next prev parent reply other threads:[~2019-08-22 15:06 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-06 10:01 [PATCH v2 00/12] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 01/12] irqchip/gic: Rework gic_configure_irq to take the full ICFGR base Marc Zyngier
2019-08-19 14:26 ` Zenghui Yu
2019-08-19 14:53 ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 02/12] irqchip/gic-v3: Add INTID range and convertion primitives Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 03/12] dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 04/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-19 14:25 ` Zenghui Yu
2019-08-20 9:18 ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 05/12] irqchip/gic: Prepare for more than 16 PPIs Marc Zyngier
2019-08-21 18:40 ` Zenghui Yu
2019-08-22 16:11 ` Julien
2019-08-22 16:32 ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 06/12] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts Marc Zyngier
2019-08-22 15:05 ` Julien [this message]
2019-08-06 10:01 ` [PATCH v2 07/12] irqchip/gic-v3: Dynamically allocate PPI partition descriptors Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 08/12] dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 09/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges Marc Zyngier
2019-08-06 10:15 ` Vladimir Murzin
2019-08-06 11:15 ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 11/12] irqchip/gic: Skip DT quirks when evaluating IIDR-based quirks Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 12/12] irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803 Marc Zyngier
2019-08-06 11:07 ` John Garry
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=daa0ff03-cf73-e1de-b4b2-d1382c5d5548@gmail.com \
--to=julien.thierry.kdev@gmail.com \
--cc=jason@lakedaemon.net \
--cc=john.garry@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lokeshvutla@ti.com \
--cc=maz@kernel.org \
--cc=robh+dt@kernel.org \
--cc=shameerali.kolothum.thodi@huawei.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).