From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E60CFC433EF for ; Mon, 10 Jan 2022 12:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245211AbiAJME6 (ORCPT ); Mon, 10 Jan 2022 07:04:58 -0500 Received: from foss.arm.com ([217.140.110.172]:33544 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245237AbiAJMEN (ORCPT ); Mon, 10 Jan 2022 07:04:13 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B34D42B; Mon, 10 Jan 2022 04:04:12 -0800 (PST) Received: from [10.57.85.117] (unknown [10.57.85.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D38C83F5A1; Mon, 10 Jan 2022 04:04:09 -0800 (PST) Message-ID: Date: Mon, 10 Jan 2022 12:04:07 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Re: [PATCH V2 7/7] coresight: trbe: Work around the trace data corruption To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mathieu Poirier , coresight@lists.linaro.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org References: <1641517808-5735-1-git-send-email-anshuman.khandual@arm.com> <1641517808-5735-8-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose In-Reply-To: <1641517808-5735-8-git-send-email-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. Workaround this > problem in the driver, by preventing TRBE initialization on affected cpus. > The firmware must have disabled the access to TRBE for the kernel on such > implementations. This will cover the kernel for any firmware that doesn't > do this already. This just updates the TRBE driver as required. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mathieu Poirier > Cc: Suzuki Poulose > Cc: coresight@lists.linaro.org > Cc: linux-doc@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/Kconfig | 2 +- > drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 209e481acf0d..8a2245c3e857 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -821,7 +821,7 @@ config ARM64_ERRATUM_2038923 > > config ARM64_ERRATUM_1902691 > bool "Cortex-A510: 1902691: workaround TRBE trace corruption" > - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + depends on CORESIGHT_TRBE > default y > help > This option adds the workaround for ARM Cortex-A510 erratum 1902691. > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index c4cc529749f8..d2f1c68e589c 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -93,12 +93,14 @@ struct trbe_buf { > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 > #define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 > +#define TRBE_IS_BROKEN 4 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, > [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, > + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -181,6 +183,11 @@ static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudat > return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); > } > > +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -1288,6 +1295,11 @@ static void arm_trbe_probe_cpu(void *info) > */ > trbe_check_errata(cpudata); > > + if (trbe_is_broken(cpudata)) { > + pr_err("Disabling TRBE on cpu%d due to erratum\n", cpu); > + goto cpu_clear; > + } > + > /* > * If the TRBE is affected by erratum TRBE_WORKAROUND_OVERWRITE_FILL_MODE, > * we must always program the TBRPTR_EL1, 256bytes from a page Reviewed-by: Suzuki K Poulose