Re: [PATCH v4 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018

From: Robert Marko <robimarko@gmail.com>
To: Sricharan Ramabadhran <quic_srichara@quicinc.com>,
	agross@kernel.org, andersson@kernel.org,
	konrad.dybcio@linaro.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
	sboyd@kernel.org, ulf.hansson@linaro.org,
	linus.walleij@linaro.org, catalin.marinas@arm.com,
	will@kernel.org, p.zabel@pengutronix.de,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 2/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
Date: Thu, 11 May 2023 12:55:45 +0200	[thread overview]
Message-ID: <db104b16-2d28-7e09-e195-6de5e1653ce1@gmail.com> (raw)
In-Reply-To: <20230510134121.1232286-3-quic_srichara@quicinc.com>


> +
> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> +	F(143713, P_XO, 1, 1, 167),
> +	F(400000, P_XO, 1, 1, 60),
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(48000000, P_GPLL2, 12, 1, 2),
> +	F(96000000, P_GPLL2, 12, 0, 0),
> +	F(177777778, P_GPLL0, 1, 2, 9),
> +	F(192000000, P_GPLL2, 6, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> +	.cmd_rcgr = 0x42004,
> +	.freq_tbl = ftbl_sdcc1_apps_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "sdcc1_apps_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
Hi,
SDCC clocks should be using "clk_rcg2_floor_ops" to round down and avoid 
overclocking
the cards and kernel will warn about it:
[    1.016194] mmc0: Card appears overclocked; req 52000000 Hz, actual 
96000000 Hz
[    1.016278] mmc0: Card appears overclocked; req 52000000 Hz, actual 
96000000 Hz

Regards,
Robert