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([2001:b07:6468:f312:e876:e214:dc8e:2846]) by smtp.gmail.com with ESMTPSA id a10sm13273923wrm.52.2019.10.06.09.15.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Oct 2019 09:15:36 -0700 (PDT) Subject: Re: [RFC PATCH 03/13] kvm: Add XO memslot type To: "Edgecombe, Rick P" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "peterz@infradead.org" , "keescook@chromium.org" , "Christopherson, Sean J" , "linux-mm@kvack.org" , "x86@kernel.org" , "luto@kernel.org" , "Hansen, Dave" Cc: "kristen@linux.intel.com" , "Dock, Deneen T" , "yu.c.zhang@linux.intel.com" References: <20191003212400.31130-1-rick.p.edgecombe@intel.com> <20191003212400.31130-4-rick.p.edgecombe@intel.com> <5201724e-bded-1af1-7f46-0f3e1763c797@redhat.com> <9b885e65c3ec0ab8b4de0d38f2f20686a7afe0d0.camel@intel.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Sun, 6 Oct 2019 18:15:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <9b885e65c3ec0ab8b4de0d38f2f20686a7afe0d0.camel@intel.com> Content-Language: en-US X-MC-Unique: Y9SOhPgTPF-XXqqJ66h8_g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/10/19 21:06, Edgecombe, Rick P wrote: > The reasoning was that it seems like KVM leaves it to userspace to contro= l the > physical address space layout since userspace decides the supported physi= cal > address bits and lays out memory in the physical address space. So duplic= ation > with XO memslots was an attempt was to keep the logic around that togethe= r. >=20 > I'll take another look at doing it this way though. I think userspace may= still > need to adjust the MAXPHYADDR and be aware it can't layout memory in the = XO > range. Right, you would have to use KVM_ENABLE_CAP passing the desired X bit (which must be < MAXPHYADDR) as the argument. Userspace needs to know that it must then make MAXPHYADDR in the guest CPUID equal to the argument. When the MSR is written to 1, bit "MAXPHYADDR-1" in the page table entries becomes an XO bit. Paolo