[PATCH 01/12] ASoC: amd: add Vangogh ACP5x IP register header

[PATCH 01/12] ASoC: amd: add Vangogh ACP5x IP register header

[Vijendar Mukunda]

From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

Add register header for ACP5x IP in Vangogh platform.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/vg_chip_offset_byte.h | 337 ++++++++++++++++++++
 1 file changed, 337 insertions(+)
 create mode 100644 sound/soc/amd/vangogh/vg_chip_offset_byte.h

diff --git a/sound/soc/amd/vangogh/vg_chip_offset_byte.h b/sound/soc/amd/vangogh/vg_chip_offset_byte.h
new file mode 100644
index 000000000000..b1165ae142b7
--- /dev/null
+++ b/sound/soc/amd/vangogh/vg_chip_offset_byte.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AMD ACP 5.x Register Documentation
+ *
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ */
+
+#ifndef _acp_ip_OFFSET_HEADER
+#define _acp_ip_OFFSET_HEADER
+
+/* Registers from ACP_DMA block */
+#define ACP_DMA_CNTL_0                                0x1240000
+#define ACP_DMA_CNTL_1                                0x1240004
+#define ACP_DMA_CNTL_2                                0x1240008
+#define ACP_DMA_CNTL_3                                0x124000C
+#define ACP_DMA_CNTL_4                                0x1240010
+#define ACP_DMA_CNTL_5                                0x1240014
+#define ACP_DMA_CNTL_6                                0x1240018
+#define ACP_DMA_CNTL_7                                0x124001C
+#define ACP_DMA_DSCR_STRT_IDX_0                       0x1240020
+#define ACP_DMA_DSCR_STRT_IDX_1                       0x1240024
+#define ACP_DMA_DSCR_STRT_IDX_2                       0x1240028
+#define ACP_DMA_DSCR_STRT_IDX_3                       0x124002C
+#define ACP_DMA_DSCR_STRT_IDX_4                       0x1240030
+#define ACP_DMA_DSCR_STRT_IDX_5                       0x1240034
+#define ACP_DMA_DSCR_STRT_IDX_6                       0x1240038
+#define ACP_DMA_DSCR_STRT_IDX_7                       0x124003C
+#define ACP_DMA_DSCR_CNT_0                            0x1240040
+#define ACP_DMA_DSCR_CNT_1                            0x1240044
+#define ACP_DMA_DSCR_CNT_2                            0x1240048
+#define ACP_DMA_DSCR_CNT_3                            0x124004C
+#define ACP_DMA_DSCR_CNT_4                            0x1240050
+#define ACP_DMA_DSCR_CNT_5                            0x1240054
+#define ACP_DMA_DSCR_CNT_6                            0x1240058
+#define ACP_DMA_DSCR_CNT_7                            0x124005C
+#define ACP_DMA_PRIO_0                                0x1240060
+#define ACP_DMA_PRIO_1                                0x1240064
+#define ACP_DMA_PRIO_2                                0x1240068
+#define ACP_DMA_PRIO_3                                0x124006C
+#define ACP_DMA_PRIO_4                                0x1240070
+#define ACP_DMA_PRIO_5                                0x1240074
+#define ACP_DMA_PRIO_6                                0x1240078
+#define ACP_DMA_PRIO_7                                0x124007C
+#define ACP_DMA_CUR_DSCR_0                            0x1240080
+#define ACP_DMA_CUR_DSCR_1                            0x1240084
+#define ACP_DMA_CUR_DSCR_2                            0x1240088
+#define ACP_DMA_CUR_DSCR_3                            0x124008C
+#define ACP_DMA_CUR_DSCR_4                            0x1240090
+#define ACP_DMA_CUR_DSCR_5                            0x1240094
+#define ACP_DMA_CUR_DSCR_6                            0x1240098
+#define ACP_DMA_CUR_DSCR_7                            0x124009C
+#define ACP_DMA_CUR_TRANS_CNT_0                       0x12400A0
+#define ACP_DMA_CUR_TRANS_CNT_1                       0x12400A4
+#define ACP_DMA_CUR_TRANS_CNT_2                       0x12400A8
+#define ACP_DMA_CUR_TRANS_CNT_3                       0x12400AC
+#define ACP_DMA_CUR_TRANS_CNT_4                       0x12400B0
+#define ACP_DMA_CUR_TRANS_CNT_5                       0x12400B4
+#define ACP_DMA_CUR_TRANS_CNT_6                       0x12400B8
+#define ACP_DMA_CUR_TRANS_CNT_7                       0x12400BC
+#define ACP_DMA_ERR_STS_0                             0x12400C0
+#define ACP_DMA_ERR_STS_1                             0x12400C4
+#define ACP_DMA_ERR_STS_2                             0x12400C8
+#define ACP_DMA_ERR_STS_3                             0x12400CC
+#define ACP_DMA_ERR_STS_4                             0x12400D0
+#define ACP_DMA_ERR_STS_5                             0x12400D4
+#define ACP_DMA_ERR_STS_6                             0x12400D8
+#define ACP_DMA_ERR_STS_7                             0x12400DC
+#define ACP_DMA_DESC_BASE_ADDR                        0x12400E0
+#define ACP_DMA_DESC_MAX_NUM_DSCR                     0x12400E4
+#define ACP_DMA_CH_STS                                0x12400E8
+#define ACP_DMA_CH_GROUP                              0x12400EC
+#define ACP_DMA_CH_RST_STS                            0x12400F0
+
+/* Registers from ACP_AXI2AXIATU block */
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1                0x1240C00
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1                0x1240C04
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2                0x1240C08
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2                0x1240C0C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3                0x1240C10
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3                0x1240C14
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4                0x1240C18
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4                0x1240C1C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0x1240C20
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0x1240C24
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6                0x1240C28
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6                0x1240C2C
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7                0x1240C30
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7                0x1240C34
+#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8                0x1240C38
+#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8                0x1240C3C
+#define ACPAXI2AXI_ATU_CTRL                           0x1240C40
+
+/*  Registers from ACP_CLKRST block */
+#define ACP_SOFT_RESET                                0x1241000
+#define ACP_CONTROL                                   0x1241004
+#define ACP_STATUS                                    0x1241008
+#define ACP_DYNAMIC_CG_MASTER_CONTROL                 0x1241010
+
+/* Registers from ACP_MISC block */
+#define ACP_EXTERNAL_INTR_ENB                         0x1241800
+#define ACP_EXTERNAL_INTR_CNTL                        0x1241804
+#define ACP_EXTERNAL_INTR_STAT                        0x1241808
+#define ACP_ERROR_STATUS                              0x12418C4
+#define ACP_SW_I2S_ERROR_REASON                       0x12418C8
+#define ACP_MEM_PG_STS                                0x12418CC
+#define ACP_PGMEM_DEEP_SLEEP_CTRL                     0x12418D0
+#define ACP_PGMEM_SHUT_DOWN_CTRL                      0x12418D4
+
+/* Registers from ACP_PGFSM block */
+#define ACP_PIN_CONFIG                                0x1241400
+#define ACP_PAD_PULLUP_CTRL                           0x1241404
+#define ACP_PAD_PULLDOWN_CTRL                         0x1241408
+#define ACP_PAD_DRIVE_STRENGTH_CTRL                   0x124140C
+#define ACP_PAD_SCHMEN_CTRL                           0x1241410
+#define ACP_SW_PAD_KEEPER_EN                          0x1241414
+#define ACP_SW_WAKE_EN                                0x1241418
+#define ACP_I2S_WAKE_EN                               0x124141C
+#define ACP_PME_EN                                    0x1241420
+#define ACP_PGFSM_CONTROL                             0x1241424
+#define ACP_PGFSM_STATUS                              0x1241428
+#define ACP_CLKMUX_SEL                                0x124142C
+#define ACP_DEVICE_STATE                              0x1241430
+#define AZ_DEVICE_STATE                               0x1241434
+#define ACP_INTR_URGENCY_TIMER                        0x1241438
+#define AZ_INTR_URGENCY_TIMER                         0x124143C
+#define ACP_AON_SW_INTR_TRIG                          0x1241440
+
+/* Registers from ACP_SCRATCH block */
+#define ACP_SCRATCH_REG_0                             0x1250000
+#define ACP_SCRATCH_REG_1                             0x1250004
+#define ACP_SCRATCH_REG_2                             0x1250008
+#define ACP_SCRATCH_REG_3                             0x125000C
+#define ACP_SCRATCH_REG_4                             0x1250010
+#define ACP_SCRATCH_REG_5                             0x1250014
+#define ACP_SCRATCH_REG_6                             0x1250018
+#define ACP_SCRATCH_REG_7                             0x125001C
+#define ACP_SCRATCH_REG_8                             0x1250020
+#define ACP_SCRATCH_REG_9                             0x1250024
+#define ACP_SCRATCH_REG_10                            0x1250028
+#define ACP_SCRATCH_REG_11                            0x125002C
+#define ACP_SCRATCH_REG_12                            0x1250030
+#define ACP_SCRATCH_REG_13                            0x1250034
+#define ACP_SCRATCH_REG_14                            0x1250038
+#define ACP_SCRATCH_REG_15                            0x125003C
+#define ACP_SCRATCH_REG_16                            0x1250040
+#define ACP_SCRATCH_REG_17                            0x1250044
+#define ACP_SCRATCH_REG_18                            0x1250048
+#define ACP_SCRATCH_REG_19                            0x125004C
+#define ACP_SCRATCH_REG_20                            0x1250050
+#define ACP_SCRATCH_REG_21                            0x1250054
+#define ACP_SCRATCH_REG_22                            0x1250058
+#define ACP_SCRATCH_REG_23                            0x125005C
+#define ACP_SCRATCH_REG_24                            0x1250060
+#define ACP_SCRATCH_REG_25                            0x1250064
+#define ACP_SCRATCH_REG_26                            0x1250068
+#define ACP_SCRATCH_REG_27                            0x125006C
+#define ACP_SCRATCH_REG_28                            0x1250070
+#define ACP_SCRATCH_REG_29                            0x1250074
+#define ACP_SCRATCH_REG_30                            0x1250078
+#define ACP_SCRATCH_REG_31                            0x125007C
+#define ACP_SCRATCH_REG_32                            0x1250080
+#define ACP_SCRATCH_REG_33                            0x1250084
+#define ACP_SCRATCH_REG_34                            0x1250088
+#define ACP_SCRATCH_REG_35                            0x125008C
+#define ACP_SCRATCH_REG_36                            0x1250090
+#define ACP_SCRATCH_REG_37                            0x1250094
+#define ACP_SCRATCH_REG_38                            0x1250098
+#define ACP_SCRATCH_REG_39                            0x125009C
+#define ACP_SCRATCH_REG_40                            0x12500A0
+#define ACP_SCRATCH_REG_41                            0x12500A4
+#define ACP_SCRATCH_REG_42                            0x12500A8
+#define ACP_SCRATCH_REG_43                            0x12500AC
+#define ACP_SCRATCH_REG_44                            0x12500B0
+#define ACP_SCRATCH_REG_45                            0x12500B4
+#define ACP_SCRATCH_REG_46                            0x12500B8
+#define ACP_SCRATCH_REG_47                            0x12500BC
+#define ACP_SCRATCH_REG_48                            0x12500C0
+#define ACP_SCRATCH_REG_49                            0x12500C4
+#define ACP_SCRATCH_REG_50                            0x12500C8
+#define ACP_SCRATCH_REG_51                            0x12500CC
+#define ACP_SCRATCH_REG_52                            0x12500D0
+#define ACP_SCRATCH_REG_53                            0x12500D4
+#define ACP_SCRATCH_REG_54                            0x12500D8
+#define ACP_SCRATCH_REG_55                            0x12500DC
+#define ACP_SCRATCH_REG_56                            0x12500E0
+#define ACP_SCRATCH_REG_57                            0x12500E4
+#define ACP_SCRATCH_REG_58                            0x12500E8
+#define ACP_SCRATCH_REG_59                            0x12500EC
+#define ACP_SCRATCH_REG_60                            0x12500F0
+#define ACP_SCRATCH_REG_61                            0x12500F4
+#define ACP_SCRATCH_REG_62                            0x12500F8
+#define ACP_SCRATCH_REG_63                            0x12500FC
+#define ACP_SCRATCH_REG_64                            0x1250100
+#define ACP_SCRATCH_REG_65                            0x1250104
+#define ACP_SCRATCH_REG_66                            0x1250108
+#define ACP_SCRATCH_REG_67                            0x125010C
+#define ACP_SCRATCH_REG_68                            0x1250110
+#define ACP_SCRATCH_REG_69                            0x1250114
+#define ACP_SCRATCH_REG_70                            0x1250118
+#define ACP_SCRATCH_REG_71                            0x125011C
+#define ACP_SCRATCH_REG_72                            0x1250120
+#define ACP_SCRATCH_REG_73                            0x1250124
+#define ACP_SCRATCH_REG_74                            0x1250128
+#define ACP_SCRATCH_REG_75                            0x125012C
+#define ACP_SCRATCH_REG_76                            0x1250130
+#define ACP_SCRATCH_REG_77                            0x1250134
+#define ACP_SCRATCH_REG_78                            0x1250138
+#define ACP_SCRATCH_REG_79                            0x125013C
+#define ACP_SCRATCH_REG_80                            0x1250140
+#define ACP_SCRATCH_REG_81                            0x1250144
+#define ACP_SCRATCH_REG_82                            0x1250148
+#define ACP_SCRATCH_REG_83                            0x125014C
+#define ACP_SCRATCH_REG_84                            0x1250150
+#define ACP_SCRATCH_REG_85                            0x1250154
+#define ACP_SCRATCH_REG_86                            0x1250158
+#define ACP_SCRATCH_REG_87                            0x125015C
+#define ACP_SCRATCH_REG_88                            0x1250160
+#define ACP_SCRATCH_REG_89                            0x1250164
+#define ACP_SCRATCH_REG_90                            0x1250168
+#define ACP_SCRATCH_REG_91                            0x125016C
+#define ACP_SCRATCH_REG_92                            0x1250170
+#define ACP_SCRATCH_REG_93                            0x1250174
+#define ACP_SCRATCH_REG_94                            0x1250178
+#define ACP_SCRATCH_REG_95                            0x125017C
+#define ACP_SCRATCH_REG_96                            0x1250180
+#define ACP_SCRATCH_REG_97                            0x1250184
+#define ACP_SCRATCH_REG_98                            0x1250188
+#define ACP_SCRATCH_REG_99                            0x125018C
+#define ACP_SCRATCH_REG_100                           0x1250190
+#define ACP_SCRATCH_REG_101                           0x1250194
+#define ACP_SCRATCH_REG_102                           0x1250198
+#define ACP_SCRATCH_REG_103                           0x125019C
+#define ACP_SCRATCH_REG_104                           0x12501A0
+#define ACP_SCRATCH_REG_105                           0x12501A4
+#define ACP_SCRATCH_REG_106                           0x12501A8
+#define ACP_SCRATCH_REG_107                           0x12501AC
+#define ACP_SCRATCH_REG_108                           0x12501B0
+#define ACP_SCRATCH_REG_109                           0x12501B4
+#define ACP_SCRATCH_REG_110                           0x12501B8
+#define ACP_SCRATCH_REG_111                           0x12501BC
+#define ACP_SCRATCH_REG_112                           0x12501C0
+#define ACP_SCRATCH_REG_113                           0x12501C4
+#define ACP_SCRATCH_REG_114                           0x12501C8
+#define ACP_SCRATCH_REG_115                           0x12501CC
+#define ACP_SCRATCH_REG_116                           0x12501D0
+#define ACP_SCRATCH_REG_117                           0x12501D4
+#define ACP_SCRATCH_REG_118                           0x12501D8
+#define ACP_SCRATCH_REG_119                           0x12501DC
+#define ACP_SCRATCH_REG_120                           0x12501E0
+#define ACP_SCRATCH_REG_121                           0x12501E4
+#define ACP_SCRATCH_REG_122                           0x12501E8
+#define ACP_SCRATCH_REG_123                           0x12501EC
+#define ACP_SCRATCH_REG_124                           0x12501F0
+#define ACP_SCRATCH_REG_125                           0x12501F4
+#define ACP_SCRATCH_REG_126                           0x12501F8
+#define ACP_SCRATCH_REG_127                           0x12501FC
+#define ACP_SCRATCH_REG_128                           0x1250200
+
+/* Registers from ACP_AUDIO_BUFFERS block */
+#define ACP_I2S_RX_RINGBUFADDR                        0x1242000
+#define ACP_I2S_RX_RINGBUFSIZE                        0x1242004
+#define ACP_I2S_RX_LINKPOSITIONCNTR                   0x1242008
+#define ACP_I2S_RX_FIFOADDR                           0x124200C
+#define ACP_I2S_RX_FIFOSIZE                           0x1242010
+#define ACP_I2S_RX_DMA_SIZE                           0x1242014
+#define ACP_I2S_RX_LINEARPOSCNTR_HIGH                 0x1242018
+#define ACP_I2S_RX_LINEARPOSCNTR_LOW                  0x124201C
+#define ACP_I2S_RX_INTR_WATERMARK_SIZE                0x1242020
+#define ACP_I2S_TX_RINGBUFADDR                        0x1242024
+#define ACP_I2S_TX_RINGBUFSIZE                        0x1242028
+#define ACP_I2S_TX_LINKPOSITIONCNTR                   0x124202C
+#define ACP_I2S_TX_FIFOADDR                           0x1242030
+#define ACP_I2S_TX_FIFOSIZE                           0x1242034
+#define ACP_I2S_TX_DMA_SIZE                           0x1242038
+#define ACP_I2S_TX_LINEARPOSCNTR_HIGH                 0x124203C
+#define ACP_I2S_TX_LINEARPOSCNTR_LOW                  0x1242040
+#define ACP_I2S_TX_INTR_WATERMARK_SIZE                0x1242044
+#define ACP_BT_RX_RINGBUFADDR                         0x1242048
+#define ACP_BT_RX_RINGBUFSIZE                         0x124204C
+#define ACP_BT_RX_LINKPOSITIONCNTR                    0x1242050
+#define ACP_BT_RX_FIFOADDR                            0x1242054
+#define ACP_BT_RX_FIFOSIZE                            0x1242058
+#define ACP_BT_RX_DMA_SIZE                            0x124205C
+#define ACP_BT_RX_LINEARPOSCNTR_HIGH                  0x1242060
+#define ACP_BT_RX_LINEARPOSCNTR_LOW                   0x1242064
+#define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x1242068
+#define ACP_BT_TX_RINGBUFADDR                         0x124206C
+#define ACP_BT_TX_RINGBUFSIZE                         0x1242070
+#define ACP_BT_TX_LINKPOSITIONCNTR                    0x1242074
+#define ACP_BT_TX_FIFOADDR                            0x1242078
+#define ACP_BT_TX_FIFOSIZE                            0x124207C
+#define ACP_BT_TX_DMA_SIZE                            0x1242080
+#define ACP_BT_TX_LINEARPOSCNTR_HIGH                  0x1242084
+#define ACP_BT_TX_LINEARPOSCNTR_LOW                   0x1242088
+#define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x124208C
+#define ACP_HS_RX_RINGBUFADDR                         0x1242090
+#define ACP_HS_RX_RINGBUFSIZE                         0x1242094
+#define ACP_HS_RX_LINKPOSITIONCNTR                    0x1242098
+#define ACP_HS_RX_FIFOADDR                            0x124209C
+#define ACP_HS_RX_FIFOSIZE                            0x12420A0
+#define ACP_HS_RX_DMA_SIZE                            0x12420A4
+#define ACP_HS_RX_LINEARPOSCNTR_HIGH	              0x12420A8
+#define ACP_HS_RX_LINEARPOSCNTR_LOW                   0x12420AC
+#define ACP_HS_RX_INTR_WATERMARK_SIZE                 0x12420B0
+#define ACP_HS_TX_RINGBUFADDR                         0x12420B4
+#define ACP_HS_TX_RINGBUFSIZE                         0x12420B8
+#define ACP_HS_TX_LINKPOSITIONCNTR                    0x12420BC
+#define ACP_HS_TX_FIFOADDR                            0x12420C0
+#define ACP_HS_TX_FIFOSIZE                            0x12420C4
+#define ACP_HS_TX_DMA_SIZE                            0x12420C8
+#define ACP_HS_TX_LINEARPOSCNTR_HIGH                  0x12420CC
+#define ACP_HS_TX_LINEARPOSCNTR_LOW                   0x12420D0
+#define ACP_HS_TX_INTR_WATERMARK_SIZE                 0x12420D4
+
+/* Registers from ACP_I2S_TDM block */
+#define ACP_I2STDM_IER                                0x1242400
+#define ACP_I2STDM_IRER                               0x1242404
+#define ACP_I2STDM_RXFRMT                             0x1242408
+#define ACP_I2STDM_ITER                               0x124240C
+#define ACP_I2STDM_TXFRMT                             0x1242410
+#define ACP_I2STDM0_MSTRCLKGEN                        0x1242414
+#define ACP_I2STDM1_MSTRCLKGEN                        0x1242418
+#define ACP_I2STDM2_MSTRCLKGEN                        0x124241C
+#define ACP_I2STDM_REFCLKGEN                          0x1242420
+
+/* Registers from ACP_BT_TDM block */
+#define ACP_BTTDM_IER                                 0x1242800
+#define ACP_BTTDM_IRER                                0x1242804
+#define ACP_BTTDM_RXFRMT                              0x1242808
+#define ACP_BTTDM_ITER                                0x124280C
+#define ACP_BTTDM_TXFRMT                              0x1242810
+#define ACP_HSTDM_IER                                 0x1242814
+#define ACP_HSTDM_IRER                                0x1242818
+#define ACP_HSTDM_RXFRMT                              0x124281C
+#define ACP_HSTDM_ITER                                0x1242820
+#define ACP_HSTDM_TXFRMT                              0x1242824
+#endif
-- 
2.17.1

[PATCH 02/12] ASoC: amd: add Vangogh ACP PCI driver

[Vijendar Mukunda]

From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

ACP is a PCI audio device.
This patch adds PCI driver to bind to this device and get
PCI resources.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x.h     | 21 ++++++++
 sound/soc/amd/vangogh/pci-acp5x.c | 87 +++++++++++++++++++++++++++++++
 2 files changed, 108 insertions(+)
 create mode 100644 sound/soc/amd/vangogh/acp5x.h
 create mode 100644 sound/soc/amd/vangogh/pci-acp5x.c

diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
new file mode 100644
index 000000000000..a5e7f7cb65a1
--- /dev/null
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AMD ALSA SoC PCM Driver
+ *
+ * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+ */
+
+#include "vg_chip_offset_byte.h"
+
+#define ACP5x_PHY_BASE_ADDRESS 0x1240000
+#define ACP_DEVICE_ID 0x15E2
+
+static inline u32 acp_readl(void __iomem *base_addr)
+{
+	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
+}
+
+static inline void acp_writel(u32 val, void __iomem *base_addr)
+{
+	writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
+}
diff --git a/sound/soc/amd/vangogh/pci-acp5x.c b/sound/soc/amd/vangogh/pci-acp5x.c
new file mode 100644
index 000000000000..e56d060a5cb9
--- /dev/null
+++ b/sound/soc/amd/vangogh/pci-acp5x.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// AMD Vangogh ACP PCI Driver
+//
+// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/io.h>
+
+#include "acp5x.h"
+
+struct acp5x_dev_data {
+	void __iomem *acp5x_base;
+};
+
+static int snd_acp5x_probe(struct pci_dev *pci,
+			   const struct pci_device_id *pci_id)
+{
+	struct acp5x_dev_data *adata;
+	int ret;
+	u32 addr;
+
+	if (pci->revision != 0x50)
+		return -ENODEV;
+
+	if (pci_enable_device(pci)) {
+		dev_err(&pci->dev, "pci_enable_device failed\n");
+		return -ENODEV;
+	}
+
+	ret = pci_request_regions(pci, "AMD ACP5x audio");
+	if (ret < 0) {
+		dev_err(&pci->dev, "pci_request_regions failed\n");
+		goto disable_pci;
+	}
+
+	adata = devm_kzalloc(&pci->dev, sizeof(struct acp5x_dev_data),
+			     GFP_KERNEL);
+	if (!adata) {
+		ret = -ENOMEM;
+		goto release_regions;
+	}
+	addr = pci_resource_start(pci, 0);
+	adata->acp5x_base = devm_ioremap(&pci->dev, addr,
+					 pci_resource_len(pci, 0));
+	if (!adata->acp5x_base) {
+		ret = -ENOMEM;
+		goto release_regions;
+	}
+	pci_set_master(pci);
+	pci_set_drvdata(pci, adata);
+
+release_regions:
+	pci_release_regions(pci);
+disable_pci:
+	pci_disable_device(pci);
+
+	return ret;
+}
+
+static void snd_acp5x_remove(struct pci_dev *pci)
+{
+	pci_release_regions(pci);
+	pci_disable_device(pci);
+}
+
+static const struct pci_device_id snd_acp5x_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
+	.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
+	.class_mask = 0xffffff },
+	{ 0, },
+};
+MODULE_DEVICE_TABLE(pci, snd_acp5x_ids);
+
+static struct pci_driver acp5x_driver  = {
+	.name = KBUILD_MODNAME,
+	.id_table = snd_acp5x_ids,
+	.probe = snd_acp5x_probe,
+	.remove = snd_acp5x_remove,
+};
+
+module_pci_driver(acp5x_driver);
+
+MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
+MODULE_DESCRIPTION("AMD Vangogh ACP PCI driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1

Re: [PATCH 02/12] ASoC: amd: add Vangogh ACP PCI driver

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 357 bytes --]

On Wed, Jul 07, 2021 at 11:26:13AM +0530, Vijendar Mukunda wrote:

> +static inline u32 acp_readl(void __iomem *base_addr)
> +{
> +	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
> +}

I see this was the same for Renoir but it's weird that the read and
write functions are substracting rather than adding the base address
here.  A comment might be good.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 02/12] ASoC: amd: add Vangogh ACP PCI driver

[Mukunda,Vijendar]

On 7/7/21 9:47 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:13AM +0530, Vijendar Mukunda wrote:
> 
>> +static inline u32 acp_readl(void __iomem *base_addr)
>> +{
>> +	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
>> +}
> 
> I see this was the same for Renoir but it's weird that the read and
> write functions are substracting rather than adding the base address
> here.  A comment might be good.
> 
We can modify code by providing relative offset from base address which
adds base address in readl and writel functions.
To make this change, we have to modify original header file.
To have sync with our HW team and Firmware teams, we are using same
common header file.

We will add comment in the code.

[PATCH 03/12] add acp5x init/de-init functions

[Vijendar Mukunda]

From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

Add Vangogh ACP PCI driver init/deinit functions.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x.h     |  12 +++
 sound/soc/amd/vangogh/pci-acp5x.c | 135 ++++++++++++++++++++++++++++++
 2 files changed, 147 insertions(+)

diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index a5e7f7cb65a1..11b555306958 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -9,6 +9,18 @@
 
 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
 #define ACP_DEVICE_ID 0x15E2
+#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001
+
+#define ACP_PGFSM_CNTL_POWER_ON_MASK	0x01
+#define ACP_PGFSM_CNTL_POWER_OFF_MASK	0x00
+#define ACP_PGFSM_STATUS_MASK		0x03
+#define ACP_POWERED_ON			0x00
+#define ACP_POWER_ON_IN_PROGRESS	0x01
+#define ACP_POWERED_OFF			0x02
+#define ACP_POWER_OFF_IN_PROGRESS	0x03
+
+#define ACP_ERR_INTR_MASK	0x20000000
+#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
 
 static inline u32 acp_readl(void __iomem *base_addr)
 {
diff --git a/sound/soc/amd/vangogh/pci-acp5x.c b/sound/soc/amd/vangogh/pci-acp5x.c
index e56d060a5cb9..dbe8fef3e294 100644
--- a/sound/soc/amd/vangogh/pci-acp5x.c
+++ b/sound/soc/amd/vangogh/pci-acp5x.c
@@ -7,13 +7,138 @@
 #include <linux/pci.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 
 #include "acp5x.h"
 
+static int acp_power_gating;
+module_param(acp_power_gating, int, 0644);
+MODULE_PARM_DESC(acp_power_gating, "acp power gating flag");
+
 struct acp5x_dev_data {
 	void __iomem *acp5x_base;
 };
 
+static int acp5x_power_on(void __iomem *acp5x_base)
+{
+	u32 val;
+	int timeout;
+
+	val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
+
+	if (val == 0)
+		return val;
+
+	if ((val & ACP_PGFSM_STATUS_MASK) !=
+				ACP_POWER_ON_IN_PROGRESS)
+		acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
+			   acp5x_base + ACP_PGFSM_CONTROL);
+	timeout = 0;
+	while (++timeout < 500) {
+		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
+		if (!val)
+			return 0;
+		udelay(1);
+	}
+	return -ETIMEDOUT;
+}
+
+static int acp5x_power_off(void __iomem *acp5x_base)
+{
+	u32 val;
+	int timeout;
+
+	acp_writel(ACP_PGFSM_CNTL_POWER_OFF_MASK,
+		   acp5x_base + ACP_PGFSM_CONTROL);
+	timeout = 0;
+	while (++timeout < 500) {
+		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
+		if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_OFF)
+			return 0;
+		udelay(1);
+	}
+	return -ETIMEDOUT;
+}
+
+static int acp5x_reset(void __iomem *acp5x_base)
+{
+	u32 val;
+	int timeout;
+
+	acp_writel(1, acp5x_base + ACP_SOFT_RESET);
+	timeout = 0;
+	while (++timeout < 500) {
+		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
+		if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
+			break;
+		cpu_relax();
+	}
+	acp_writel(0, acp5x_base + ACP_SOFT_RESET);
+	timeout = 0;
+	while (++timeout < 500) {
+		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
+		if (!val)
+			return 0;
+		cpu_relax();
+	}
+	return -ETIMEDOUT;
+}
+
+static void acp5x_enable_interrupts(void __iomem *acp5x_base)
+{
+	acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
+}
+
+static void acp5x_disable_interrupts(void __iomem *acp5x_base)
+{
+	acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
+		   ACP_EXTERNAL_INTR_STAT);
+	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
+	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
+}
+
+static int acp5x_init(void __iomem *acp5x_base)
+{
+	int ret;
+
+	/* power on */
+	ret = acp5x_power_on(acp5x_base);
+	if (ret) {
+		pr_err("ACP5x power on failed\n");
+		return ret;
+	}
+	/* Reset */
+	ret = acp5x_reset(acp5x_base);
+	if (ret) {
+		pr_err("ACP5x reset failed\n");
+		return ret;
+	}
+	acp5x_enable_interrupts(acp5x_base);
+	return 0;
+}
+
+static int acp5x_deinit(void __iomem *acp5x_base)
+{
+	int ret;
+
+	acp5x_disable_interrupts(acp5x_base);
+	/* Reset */
+	ret = acp5x_reset(acp5x_base);
+	if (ret) {
+		pr_err("ACP5x reset failed\n");
+		return ret;
+	}
+	/* power off */
+	if (acp_power_gating) {
+		ret = acp5x_power_off(acp5x_base);
+		if (ret) {
+			pr_err("ACP5x power off failed\n");
+			return ret;
+		}
+	}
+	return 0;
+}
+
 static int snd_acp5x_probe(struct pci_dev *pci,
 			   const struct pci_device_id *pci_id)
 {
@@ -50,6 +175,9 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 	}
 	pci_set_master(pci);
 	pci_set_drvdata(pci, adata);
+	ret = acp5x_init(adata->acp5x_base);
+	if (ret)
+		goto release_regions;
 
 release_regions:
 	pci_release_regions(pci);
@@ -61,6 +189,13 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 
 static void snd_acp5x_remove(struct pci_dev *pci)
 {
+	struct acp5x_dev_data *adata;
+	int ret;
+
+	adata = pci_get_drvdata(pci);
+	ret = acp5x_deinit(adata->acp5x_base);
+	if (ret)
+		dev_err(&pci->dev, "ACP de-init failed\n");
 	pci_release_regions(pci);
 	pci_disable_device(pci);
 }
-- 
2.17.1

Re: [PATCH 03/12] add acp5x init/de-init functions

[Pierre-Louis Bossart]

Missing 'ASoC: amd' prefix in commit subject?


> +static int acp5x_power_on(void __iomem *acp5x_base)
> +{
> +	u32 val;
> +	int timeout;
> +
> +	val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
> +
> +	if (val == 0)
> +		return val;
> +
> +	if ((val & ACP_PGFSM_STATUS_MASK) !=
> +				ACP_POWER_ON_IN_PROGRESS)
> +		acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
> +			   acp5x_base + ACP_PGFSM_CONTROL);
> +	timeout = 0;
> +	while (++timeout < 500) {
> +		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
> +		if (!val)

Shouldn't you use something like 
if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_ON)
for symmetry with the power-off case?

> +			return 0;
> +		udelay(1);
> +	}
> +	return -ETIMEDOUT;
> +}
> +
> +static int acp5x_power_off(void __iomem *acp5x_base)
> +{
> +	u32 val;
> +	int timeout;
> +
> +	acp_writel(ACP_PGFSM_CNTL_POWER_OFF_MASK,
> +		   acp5x_base + ACP_PGFSM_CONTROL);
> +	timeout = 0;
> +	while (++timeout < 500) {
> +		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
> +		if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_OFF)
> +			return 0;
> +		udelay(1);
> +	}
> +	return -ETIMEDOUT;
> +}
> +
> +static int acp5x_reset(void __iomem *acp5x_base)
> +{
> +	u32 val;
> +	int timeout;
> +
> +	acp_writel(1, acp5x_base + ACP_SOFT_RESET);
> +	timeout = 0;
> +	while (++timeout < 500) {
> +		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
> +		if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
> +			break;
> +		cpu_relax();
> +	}
> +	acp_writel(0, acp5x_base + ACP_SOFT_RESET);
> +	timeout = 0;
> +	while (++timeout < 500) {
> +		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
> +		if (!val)
> +			return 0;
> +		cpu_relax();
> +	}
> +	return -ETIMEDOUT;
> +}
> +
> +static void acp5x_enable_interrupts(void __iomem *acp5x_base)
> +{
> +	acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
> +}
> +
> +static void acp5x_disable_interrupts(void __iomem *acp5x_base)
> +{
> +	acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
> +		   ACP_EXTERNAL_INTR_STAT);
> +	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
> +	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
> +}
> +
> +static int acp5x_init(void __iomem *acp5x_base)
> +{
> +	int ret;
> +
> +	/* power on */
> +	ret = acp5x_power_on(acp5x_base);
> +	if (ret) {
> +		pr_err("ACP5x power on failed\n");
> +		return ret;
> +	}
> +	/* Reset */
> +	ret = acp5x_reset(acp5x_base);
> +	if (ret) {
> +		pr_err("ACP5x reset failed\n");
> +		return ret;
> +	}
> +	acp5x_enable_interrupts(acp5x_base);
> +	return 0;
> +}
> +
> +static int acp5x_deinit(void __iomem *acp5x_base)
> +{
> +	int ret;
> +
> +	acp5x_disable_interrupts(acp5x_base);
> +	/* Reset */
> +	ret = acp5x_reset(acp5x_base);
> +	if (ret) {
> +		pr_err("ACP5x reset failed\n");
> +		return ret;
> +	}
> +	/* power off */
> +	if (acp_power_gating) {
> +		ret = acp5x_power_off(acp5x_base);
> +		if (ret) {
> +			pr_err("ACP5x power off failed\n");
> +			return ret;
> +		}
> +	}
> +	return 0;

shouldn't you have a sequence for shutdown that ignores the acp_power_gating parameter?

Re: [PATCH 03/12] add acp5x init/de-init functions

[Mukunda,Vijendar]

On 7/7/21 9:45 PM, Pierre-Louis Bossart wrote:
> Missing 'ASoC: amd' prefix in commit subject?
Will add prefix.
> 
> 
>> +static int acp5x_power_on(void __iomem *acp5x_base)
>> +{
>> +	u32 val;
>> +	int timeout;
>> +
>> +	val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
>> +
>> +	if (val == 0)
>> +		return val;
>> +
>> +	if ((val & ACP_PGFSM_STATUS_MASK) !=
>> +				ACP_POWER_ON_IN_PROGRESS)
>> +		acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
>> +			   acp5x_base + ACP_PGFSM_CONTROL);
>> +	timeout = 0;
>> +	while (++timeout < 500) {
>> +		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
>> +		if (!val)
> 
> Shouldn't you use something like 
> if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_ON)
> for symmetry with the power-off case?
Yes we can do that. will fix it.
> 
>> +			return 0;
>> +		udelay(1);
>> +	}
>> +	return -ETIMEDOUT;
>> +}
>> +
>> +static int acp5x_power_off(void __iomem *acp5x_base)
>> +{
>> +	u32 val;
>> +	int timeout;
>> +
>> +	acp_writel(ACP_PGFSM_CNTL_POWER_OFF_MASK,
>> +		   acp5x_base + ACP_PGFSM_CONTROL);
>> +	timeout = 0;
>> +	while (++timeout < 500) {
>> +		val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
>> +		if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_OFF)
>> +			return 0;
>> +		udelay(1);
>> +	}
>> +	return -ETIMEDOUT;
>> +}
>> +
>> +static int acp5x_reset(void __iomem *acp5x_base)
>> +{
>> +	u32 val;
>> +	int timeout;
>> +
>> +	acp_writel(1, acp5x_base + ACP_SOFT_RESET);
>> +	timeout = 0;
>> +	while (++timeout < 500) {
>> +		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
>> +		if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
>> +			break;
>> +		cpu_relax();
>> +	}
>> +	acp_writel(0, acp5x_base + ACP_SOFT_RESET);
>> +	timeout = 0;
>> +	while (++timeout < 500) {
>> +		val = acp_readl(acp5x_base + ACP_SOFT_RESET);
>> +		if (!val)
>> +			return 0;
>> +		cpu_relax();
>> +	}
>> +	return -ETIMEDOUT;
>> +}
>> +
>> +static void acp5x_enable_interrupts(void __iomem *acp5x_base)
>> +{
>> +	acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
>> +}
>> +
>> +static void acp5x_disable_interrupts(void __iomem *acp5x_base)
>> +{
>> +	acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
>> +		   ACP_EXTERNAL_INTR_STAT);
>> +	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
>> +	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
>> +}
>> +
>> +static int acp5x_init(void __iomem *acp5x_base)
>> +{
>> +	int ret;
>> +
>> +	/* power on */
>> +	ret = acp5x_power_on(acp5x_base);
>> +	if (ret) {
>> +		pr_err("ACP5x power on failed\n");
>> +		return ret;
>> +	}
>> +	/* Reset */
>> +	ret = acp5x_reset(acp5x_base);
>> +	if (ret) {
>> +		pr_err("ACP5x reset failed\n");
>> +		return ret;
>> +	}
>> +	acp5x_enable_interrupts(acp5x_base);
>> +	return 0;
>> +}
>> +
>> +static int acp5x_deinit(void __iomem *acp5x_base)
>> +{
>> +	int ret;
>> +
>> +	acp5x_disable_interrupts(acp5x_base);
>> +	/* Reset */
>> +	ret = acp5x_reset(acp5x_base);
>> +	if (ret) {
>> +		pr_err("ACP5x reset failed\n");
>> +		return ret;
>> +	}
>> +	/* power off */
>> +	if (acp_power_gating) {
>> +		ret = acp5x_power_off(acp5x_base);
>> +		if (ret) {
>> +			pr_err("ACP5x power off failed\n");
>> +			return ret;
>> +		}
>> +	}
>> +	return 0;
> 
> shouldn't you have a sequence for shutdown that ignores the acp_power_gating parameter?
>
BIOS will apply ACP Power gating(which is part of ACP power off
sequence) when ACP enters D3 state. i.e BIOS will control ACP Power gating.

acp5x_power_off() API is no longer required.This was implemented to
verify ACP Power gating during initial driver bring up.

We will drop acp5x_power_off() API, will remove acp_power_gating
parameter and post the new version.

[PATCH 04/12] ASoC: amd: create acp5x platform devices

[Vijendar Mukunda]

From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

ACP5.x IP has multiple I2S controllers and DMA controller.
Create platform devices for I2S HS controller instance, I2S SP controller
instance and DMA contrller.
Pass PCI resources like MMIO, irq to these platform devices.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x.h     | 10 ++++
 sound/soc/amd/vangogh/pci-acp5x.c | 95 ++++++++++++++++++++++++++++++-
 2 files changed, 102 insertions(+), 3 deletions(-)

diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 11b555306958..365e80b56ff9 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -22,6 +22,16 @@
 #define ACP_ERR_INTR_MASK	0x20000000
 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
 
+#define ACP5x_DEVS 0x03
+#define	ACP5x_REG_START	0x1240000
+#define	ACP5x_REG_END	0x1250200
+#define ACP5x_I2STDM_REG_START	0x1242400
+#define ACP5x_I2STDM_REG_END	0x1242410
+#define ACP5x_HS_TDM_REG_START	0x1242814
+#define ACP5x_HS_TDM_REG_END	0x1242824
+#define I2S_MODE 0x00
+#define ACP5x_I2S_MODE 0x00
+
 static inline u32 acp_readl(void __iomem *base_addr)
 {
 	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
diff --git a/sound/soc/amd/vangogh/pci-acp5x.c b/sound/soc/amd/vangogh/pci-acp5x.c
index dbe8fef3e294..2779423f7cd3 100644
--- a/sound/soc/amd/vangogh/pci-acp5x.c
+++ b/sound/soc/amd/vangogh/pci-acp5x.c
@@ -8,6 +8,8 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
 
 #include "acp5x.h"
 
@@ -17,6 +19,9 @@ MODULE_PARM_DESC(acp_power_gating, "acp power gating flag");
 
 struct acp5x_dev_data {
 	void __iomem *acp5x_base;
+	bool acp5x_audio_mode;
+	struct resource *res;
+	struct platform_device *pdev[3];
 };
 
 static int acp5x_power_on(void __iomem *acp5x_base)
@@ -143,9 +148,12 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 			   const struct pci_device_id *pci_id)
 {
 	struct acp5x_dev_data *adata;
-	int ret;
-	u32 addr;
+	struct platform_device_info pdevinfo[3];
+	unsigned int irqflags;
+	int ret, i;
+	u32 addr, val;
 
+	irqflags = IRQF_SHARED;
 	if (pci->revision != 0x50)
 		return -ENODEV;
 
@@ -179,6 +187,83 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 	if (ret)
 		goto release_regions;
 
+	val = acp_readl(adata->acp5x_base + ACP_PIN_CONFIG);
+	switch (val) {
+	case I2S_MODE:
+		adata->res = devm_kzalloc(&pci->dev,
+					  sizeof(struct resource) * 4,
+					  GFP_KERNEL);
+		if (!adata->res) {
+			ret = -ENOMEM;
+			goto de_init;
+		}
+
+		adata->res[0].name = "acp5x_i2s_iomem";
+		adata->res[0].flags = IORESOURCE_MEM;
+		adata->res[0].start = addr;
+		adata->res[0].end = addr + (ACP5x_REG_END - ACP5x_REG_START);
+
+		adata->res[1].name = "acp5x_i2s_sp";
+		adata->res[1].flags = IORESOURCE_MEM;
+		adata->res[1].start = addr + ACP5x_I2STDM_REG_START;
+		adata->res[1].end = addr + ACP5x_I2STDM_REG_END;
+
+		adata->res[2].name = "acp5x_i2s_hs";
+		adata->res[2].flags = IORESOURCE_MEM;
+		adata->res[2].start = addr + ACP5x_HS_TDM_REG_START;
+		adata->res[2].end = addr + ACP5x_HS_TDM_REG_END;
+
+		adata->res[3].name = "acp5x_i2s_irq";
+		adata->res[3].flags = IORESOURCE_IRQ;
+		adata->res[3].start = pci->irq;
+		adata->res[3].end = adata->res[3].start;
+
+		adata->acp5x_audio_mode = ACP5x_I2S_MODE;
+
+		memset(&pdevinfo, 0, sizeof(pdevinfo));
+		pdevinfo[0].name = "acp5x_i2s_dma";
+		pdevinfo[0].id = 0;
+		pdevinfo[0].parent = &pci->dev;
+		pdevinfo[0].num_res = 4;
+		pdevinfo[0].res = &adata->res[0];
+		pdevinfo[0].data = &irqflags;
+		pdevinfo[0].size_data = sizeof(irqflags);
+
+		pdevinfo[1].name = "acp5x_i2s_playcap";
+		pdevinfo[1].id = 0;
+		pdevinfo[1].parent = &pci->dev;
+		pdevinfo[1].num_res = 1;
+		pdevinfo[1].res = &adata->res[1];
+
+		pdevinfo[2].name = "acp5x_i2s_playcap";
+		pdevinfo[2].id = 1;
+		pdevinfo[2].parent = &pci->dev;
+		pdevinfo[2].num_res = 1;
+		pdevinfo[2].res = &adata->res[2];
+
+		for (i = 0; i < ACP5x_DEVS; i++) {
+			adata->pdev[i] =
+				platform_device_register_full(&pdevinfo[i]);
+			if (IS_ERR(adata->pdev[i])) {
+				dev_err(&pci->dev, "cannot register %s device\n",
+					pdevinfo[i].name);
+				ret = PTR_ERR(adata->pdev[i]);
+				goto unregister_devs;
+			}
+		}
+		break;
+	default:
+		dev_info(&pci->dev, "ACP audio mode : %d\n", val);
+	}
+	return 0;
+
+unregister_devs:
+	if (val == I2S_MODE)
+		for (i = 0; i < ACP5x_DEVS; i++)
+			platform_device_unregister(adata->pdev[i]);
+de_init:
+	if (acp5x_deinit(adata->acp5x_base))
+		dev_err(&pci->dev, "ACP de-init failed\n");
 release_regions:
 	pci_release_regions(pci);
 disable_pci:
@@ -190,9 +275,13 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 static void snd_acp5x_remove(struct pci_dev *pci)
 {
 	struct acp5x_dev_data *adata;
-	int ret;
+	int i, ret;
 
 	adata = pci_get_drvdata(pci);
+	if (adata->acp5x_audio_mode == ACP5x_I2S_MODE) {
+		for (i = 0; i < ACP5x_DEVS; i++)
+			platform_device_unregister(adata->pdev[i]);
+	}
 	ret = acp5x_deinit(adata->acp5x_base);
 	if (ret)
 		dev_err(&pci->dev, "ACP de-init failed\n");
-- 
2.17.1

Re: [PATCH 04/12] ASoC: amd: create acp5x platform devices

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 505 bytes --]

On Wed, Jul 07, 2021 at 11:26:15AM +0530, Vijendar Mukunda wrote:

> +#define I2S_MODE 0x00
> +#define ACP5x_I2S_MODE 0x00

All the other constants are namespaced so why the plain I2S_MODE?

> +	val = acp_readl(adata->acp5x_base + ACP_PIN_CONFIG);
> +	switch (val) {
> +	case I2S_MODE:

...

> +		break;
> +	default:
> +		dev_info(&pci->dev, "ACP audio mode : %d\n", val);
> +	}

Given that anything other than I2S is basically unhandled should we
perhaps print an error rather than just an info message?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 04/12] ASoC: amd: create acp5x platform devices

[Mukunda,Vijendar]

On 7/7/21 9:52 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:15AM +0530, Vijendar Mukunda wrote:
> 
>> +#define I2S_MODE 0x00
>> +#define ACP5x_I2S_MODE 0x00
> 
> All the other constants are namespaced so why the plain I2S_MODE?

Already we have defined ACP5x_I2S_MODE to check whether ACP Audio mode
is set to I2S or not.
I2S_MODE macro to match one of the value of ACP_PIN_CONFIG which will be
programmed from BIOS based on Audio Configuration.
When few other audio modes added, will move ACP_PIN_CONFIG macro
definitions to enum.

> 
>> +	val = acp_readl(adata->acp5x_base + ACP_PIN_CONFIG);
>> +	switch (val) {
>> +	case I2S_MODE:
> 
> ...
> 
>> +		break;
>> +	default:
>> +		dev_info(&pci->dev, "ACP audio mode : %d\n", val);
>> +	}
> 
> Given that anything other than I2S is basically unhandled should we
> perhaps print an error rather than just an info message
> 

As mentioned above, ACP IP also supports other audio configurations.
When other audio configuration is selected, ACP PCI driver should be
loaded. see - efb38304c(ASoC: amd: support other audio modes for raven)

[PATCH 05/12] ASoC: amd: add ACP5x PCM platform driver

[Vijendar Mukunda]

PCM platform driver binds to the platform device created by
ACP5x PCI device. PCM driver registers ALSA DMA components
with ASoC framework.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-pcm-dma.c | 79 +++++++++++++++++++++++++++
 sound/soc/amd/vangogh/acp5x.h         |  4 ++
 2 files changed, 83 insertions(+)
 create mode 100644 sound/soc/amd/vangogh/acp5x-pcm-dma.c

diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
new file mode 100644
index 000000000000..efcf01eb89ae
--- /dev/null
+++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// AMD ALSA SoC PCM Driver
+//
+// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+
+#include "acp5x.h"
+
+#define DRV_NAME "acp5x_i2s_dma"
+
+static const struct snd_soc_component_driver acp5x_i2s_component = {
+	.name		= DRV_NAME,
+};
+
+static int acp5x_audio_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct i2s_dev_data *adata;
+	int status;
+
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "platform_data not retrieved\n");
+		return -ENODEV;
+	}
+	irqflags = *((unsigned int *)(pdev->dev.platform_data));
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
+			return -ENODEV;
+	}
+
+	adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
+	if (!adata)
+		return -ENOMEM;
+
+	adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
+					 resource_size(res));
+	if (!adata->acp5x_base)
+		return -ENOMEM;
+	dev_set_drvdata(&pdev->dev, adata);
+	status = devm_snd_soc_register_component(&pdev->dev,
+						 &acp5x_i2s_component,
+						 NULL, 0);
+	if (status) {
+		dev_err(&pdev->dev, "Fail to register acp i2s component\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int acp5x_audio_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver acp5x_dma_driver = {
+	.probe = acp5x_audio_probe,
+	.remove = acp5x_audio_remove,
+	.driver = {
+		.name = "acp5x_i2s_dma",
+	},
+};
+
+module_platform_driver(acp5x_dma_driver);
+
+MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
+MODULE_DESCRIPTION("AMD ACP 5.x PCM Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 365e80b56ff9..eca642614b4f 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -32,6 +32,10 @@
 #define I2S_MODE 0x00
 #define ACP5x_I2S_MODE 0x00
 
+struct i2s_dev_data {
+	void __iomem *acp5x_base;
+};
+
 static inline u32 acp_readl(void __iomem *base_addr)
 {
 	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
-- 
2.17.1

Re: [PATCH 05/12] ASoC: amd: add ACP5x PCM platform driver

[Pierre-Louis Bossart]

> +static int acp5x_audio_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

can this be removed here and...
> +
> +static struct platform_driver acp5x_dma_driver = {
> +	.probe = acp5x_audio_probe,
> +	.remove = acp5x_audio_remove,

... here?

> +	.driver = {
> +		.name = "acp5x_i2s_dma",
> +	},
> +};

Re: [PATCH 05/12] ASoC: amd: add ACP5x PCM platform driver

[Mukunda,Vijendar]

On 7/7/21 9:47 PM, Pierre-Louis Bossart wrote:
> 
>> +static int acp5x_audio_remove(struct platform_device *pdev)
>> +{
>> +	return 0;
>> +}
> 
> can this be removed here and...

will remove it.
>> +
>> +static struct platform_driver acp5x_dma_driver = {
>> +	.probe = acp5x_audio_probe,
>> +	.remove = acp5x_audio_remove,
> 
> ... here?
> 
will fix it and post the new version.
>> +	.driver = {
>> +		.name = "acp5x_i2s_dma",
>> +	},
>> +};

Re: [PATCH 05/12] ASoC: amd: add ACP5x PCM platform driver

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 188 bytes --]

On Wed, Jul 07, 2021 at 11:26:16AM +0530, Vijendar Mukunda wrote:

> +static int acp5x_audio_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

Just drop this since it's empty.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 05/12] ASoC: amd: add ACP5x PCM platform driver

[Mukunda,Vijendar]

On 7/7/21 9:54 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:16AM +0530, Vijendar Mukunda wrote:
> 
>> +static int acp5x_audio_remove(struct platform_device *pdev)
>> +{
>> +	return 0;
>> +}
> 
> Just drop this since it's empty.
> 
Will drop the code and post the new version.

[PATCH 06/12] ASoC: amd: irq handler changes for ACP5x PCM dma driver

[Vijendar Mukunda]

Whenever audio data equal to the I2S FIFO watermark level are
produced/consumed, interrupt is generated.
Acknowledge the interrupt.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-pcm-dma.c | 62 +++++++++++++++++++++++++++
 sound/soc/amd/vangogh/acp5x.h         |  9 ++++
 2 files changed, 71 insertions(+)

diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
index efcf01eb89ae..d79712587d30 100644
--- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
+++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
@@ -21,10 +21,58 @@ static const struct snd_soc_component_driver acp5x_i2s_component = {
 	.name		= DRV_NAME,
 };
 
+static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
+{
+	struct i2s_dev_data *vg_i2s_data;
+	u16 play_flag, cap_flag;
+	u32 val;
+
+	vg_i2s_data = dev_id;
+	if (!vg_i2s_data)
+		return IRQ_NONE;
+
+	play_flag = 0;
+	cap_flag = 0;
+	val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
+	if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
+		acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
+			   ACP_EXTERNAL_INTR_STAT);
+		snd_pcm_period_elapsed(vg_i2s_data->play_stream);
+		play_flag = 1;
+	}
+	if ((val & BIT(I2S_TX_THRESHOLD)) &&
+	    vg_i2s_data->i2ssp_play_stream) {
+		acp_writel(BIT(I2S_TX_THRESHOLD),
+			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
+		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
+		play_flag = 1;
+	}
+
+	if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
+		acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
+			   ACP_EXTERNAL_INTR_STAT);
+		snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
+		cap_flag = 1;
+	}
+	if ((val & BIT(I2S_RX_THRESHOLD)) &&
+	    vg_i2s_data->i2ssp_capture_stream) {
+		acp_writel(BIT(I2S_RX_THRESHOLD),
+			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
+		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
+		cap_flag = 1;
+	}
+
+	if (play_flag | cap_flag)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
 static int acp5x_audio_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct i2s_dev_data *adata;
+	unsigned int irqflags;
 	int status;
 
 	if (!pdev->dev.platform_data) {
@@ -47,6 +95,14 @@ static int acp5x_audio_probe(struct platform_device *pdev)
 					 resource_size(res));
 	if (!adata->acp5x_base)
 		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
+		return -ENODEV;
+	}
+
+	adata->i2s_irq = res->start;
 	dev_set_drvdata(&pdev->dev, adata);
 	status = devm_snd_soc_register_component(&pdev->dev,
 						 &acp5x_i2s_component,
@@ -55,6 +111,12 @@ static int acp5x_audio_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "Fail to register acp i2s component\n");
 		return -ENODEV;
 	}
+	status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
+				  irqflags, "ACP5x_I2S_IRQ", adata);
+	if (status) {
+		dev_err(&pdev->dev, "ACP5x I2S IRQ request failed\n");
+		return -ENODEV;
+	}
 	return 0;
 }
 
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index eca642614b4f..44662e54bd34 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -31,9 +31,18 @@
 #define ACP5x_HS_TDM_REG_END	0x1242824
 #define I2S_MODE 0x00
 #define ACP5x_I2S_MODE 0x00
+#define	I2S_RX_THRESHOLD 27
+#define	I2S_TX_THRESHOLD 28
+#define	HS_TX_THRESHOLD 24
+#define	HS_RX_THRESHOLD 23
 
 struct i2s_dev_data {
+	unsigned int i2s_irq;
 	void __iomem *acp5x_base;
+	struct snd_pcm_substream *play_stream;
+	struct snd_pcm_substream *capture_stream;
+	struct snd_pcm_substream *i2ssp_play_stream;
+	struct snd_pcm_substream *i2ssp_capture_stream;
 };
 
 static inline u32 acp_readl(void __iomem *base_addr)
-- 
2.17.1

Re: [PATCH 06/12] ASoC: amd: irq handler changes for ACP5x PCM dma driver

[Pierre-Louis Bossart]

> +static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
> +{
> +	struct i2s_dev_data *vg_i2s_data;
> +	u16 play_flag, cap_flag;
> +	u32 val;
> +
> +	vg_i2s_data = dev_id;
> +	if (!vg_i2s_data)
> +		return IRQ_NONE;
> +
> +	play_flag = 0;
> +	cap_flag = 0;
> +	val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
> +	if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
> +		acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
> +			   ACP_EXTERNAL_INTR_STAT);
> +		snd_pcm_period_elapsed(vg_i2s_data->play_stream);
> +		play_flag = 1;
> +	}
> +	if ((val & BIT(I2S_TX_THRESHOLD)) &&
> +	    vg_i2s_data->i2ssp_play_stream) {
> +		acp_writel(BIT(I2S_TX_THRESHOLD),
> +			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
> +		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
> +		play_flag = 1;
> +	}
> +
> +	if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
> +		acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
> +			   ACP_EXTERNAL_INTR_STAT);
> +		snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
> +		cap_flag = 1;
> +	}
> +	if ((val & BIT(I2S_RX_THRESHOLD)) &&
> +	    vg_i2s_data->i2ssp_capture_stream) {
> +		acp_writel(BIT(I2S_RX_THRESHOLD),
> +			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
> +		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
> +		cap_flag = 1;
> +	}
> +
> +	if (play_flag | cap_flag)

it doesn't seem terribly useful to use two variables if you can use one?

> +		return IRQ_HANDLED;
> +	else
> +		return IRQ_NONE;
> +}
> +

Re: [PATCH 06/12] ASoC: amd: irq handler changes for ACP5x PCM dma driver

[Mukunda,Vijendar]

On 7/7/21 9:50 PM, Pierre-Louis Bossart wrote:
> 
>> +static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
>> +{
>> +	struct i2s_dev_data *vg_i2s_data;
>> +	u16 play_flag, cap_flag;
>> +	u32 val;
>> +
>> +	vg_i2s_data = dev_id;
>> +	if (!vg_i2s_data)
>> +		return IRQ_NONE;
>> +
>> +	play_flag = 0;
>> +	cap_flag = 0;
>> +	val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
>> +	if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
>> +		acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
>> +			   ACP_EXTERNAL_INTR_STAT);
>> +		snd_pcm_period_elapsed(vg_i2s_data->play_stream);
>> +		play_flag = 1;
>> +	}
>> +	if ((val & BIT(I2S_TX_THRESHOLD)) &&
>> +	    vg_i2s_data->i2ssp_play_stream) {
>> +		acp_writel(BIT(I2S_TX_THRESHOLD),
>> +			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
>> +		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
>> +		play_flag = 1;
>> +	}
>> +
>> +	if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
>> +		acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
>> +			   ACP_EXTERNAL_INTR_STAT);
>> +		snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
>> +		cap_flag = 1;
>> +	}
>> +	if ((val & BIT(I2S_RX_THRESHOLD)) &&
>> +	    vg_i2s_data->i2ssp_capture_stream) {
>> +		acp_writel(BIT(I2S_RX_THRESHOLD),
>> +			   vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
>> +		snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
>> +		cap_flag = 1;
>> +	}
>> +
>> +	if (play_flag | cap_flag)
> 
> it doesn't seem terribly useful to use two variables if you can use one?

Agreed. Will fix it and post the new version.
> 
>> +		return IRQ_HANDLED;
>> +	else
>> +		return IRQ_NONE;
>> +}
>> +
> 

[PATCH 07/12] ASoC: amd: add ACP5x pcm dma driver ops

[Vijendar Mukunda]

This patch adds ACP5x PCM driver DMA operations.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
 sound/soc/amd/vangogh/acp5x.h         | 106 +++++++++
 2 files changed, 410 insertions(+), 2 deletions(-)

diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
index d79712587d30..a4235cf33548 100644
--- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
+++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
@@ -17,8 +17,42 @@
 
 #define DRV_NAME "acp5x_i2s_dma"
 
-static const struct snd_soc_component_driver acp5x_i2s_component = {
-	.name		= DRV_NAME,
+static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER |
+		SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+	.formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |
+		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+	.channels_min = 2,
+	.channels_max = 2,
+	.rates = SNDRV_PCM_RATE_8000_96000,
+	.rate_min = 8000,
+	.rate_max = 96000,
+	.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
+	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+	.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
+	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
+	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp5x_pcm_hardware_capture = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER |
+		SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+	.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+	.channels_min = 2,
+	.channels_max = 2,
+	.rates = SNDRV_PCM_RATE_8000_96000,
+	.rate_min = 8000,
+	.rate_max = 96000,
+	.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
+	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+	.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
+	.periods_min = CAPTURE_MIN_NUM_PERIODS,
+	.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
@@ -68,6 +102,274 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
 		return IRQ_NONE;
 }
 
+static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
+{
+	u16 page_idx;
+	u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
+	u32 reg_dma_size, reg_fifo_size;
+	dma_addr_t addr;
+
+	addr = rtd->dma_addr;
+	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			val = ACP_SRAM_HS_PB_PTE_OFFSET;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			val = ACP_SRAM_SP_PB_PTE_OFFSET;
+		}
+	} else {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			val = ACP_SRAM_HS_CP_PTE_OFFSET;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			val = ACP_SRAM_SP_CP_PTE_OFFSET;
+		}
+	}
+	/* Group Enable */
+	acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
+		   ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
+	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
+		   ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
+
+	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
+		/* Load the low address of page int ACP SRAM through SRBM */
+		low = lower_32_bits(addr);
+		high = upper_32_bits(addr);
+
+		acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
+		high |= BIT(31);
+		acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
+			   + 4);
+		/* Move to next physically contiguous page */
+		val += 8;
+		addr += PAGE_SIZE;
+	}
+
+	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_dma_size = ACP_HS_TX_DMA_SIZE;
+			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+					HS_PB_FIFO_ADDR_OFFSET;
+			reg_fifo_addr = ACP_HS_TX_FIFOADDR;
+			reg_fifo_size = ACP_HS_TX_FIFOSIZE;
+			acp_writel(I2S_HS_TX_MEM_WINDOW_START,
+				   rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
+			break;
+
+		case I2S_SP_INSTANCE:
+		default:
+			reg_dma_size = ACP_I2S_TX_DMA_SIZE;
+			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+					SP_PB_FIFO_ADDR_OFFSET;
+			reg_fifo_addr =	ACP_I2S_TX_FIFOADDR;
+			reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
+			acp_writel(I2S_SP_TX_MEM_WINDOW_START,
+				   rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
+		}
+	} else {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_dma_size = ACP_HS_RX_DMA_SIZE;
+			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+					HS_CAPT_FIFO_ADDR_OFFSET;
+			reg_fifo_addr = ACP_HS_RX_FIFOADDR;
+			reg_fifo_size = ACP_HS_RX_FIFOSIZE;
+			acp_writel(I2S_HS_RX_MEM_WINDOW_START,
+				   rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
+			break;
+
+		case I2S_SP_INSTANCE:
+		default:
+			reg_dma_size = ACP_I2S_RX_DMA_SIZE;
+			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+					SP_CAPT_FIFO_ADDR_OFFSET;
+			reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
+			reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
+			acp_writel(I2S_SP_RX_MEM_WINDOW_START,
+				   rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
+		}
+	}
+	acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
+	acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
+	acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
+	acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
+		   | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
+		   rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
+}
+
+static int acp5x_dma_open(struct snd_soc_component *component,
+			  struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime;
+	struct snd_soc_pcm_runtime *prtd;
+	struct i2s_dev_data *adata;
+	struct i2s_stream_instance *i2s_data;
+	int ret;
+
+	runtime = substream->runtime;
+	prtd = asoc_substream_to_rtd(substream);
+	component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+	adata = dev_get_drvdata(component->dev);
+
+	i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
+	if (!i2s_data)
+		return -EINVAL;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		runtime->hw = acp5x_pcm_hardware_playback;
+	else
+		runtime->hw = acp5x_pcm_hardware_capture;
+
+	ret = snd_pcm_hw_constraint_integer(runtime,
+					    SNDRV_PCM_HW_PARAM_PERIODS);
+	if (ret < 0) {
+		dev_err(component->dev, "set integer constraint failed\n");
+		kfree(i2s_data);
+		return ret;
+	}
+	i2s_data->acp5x_base = adata->acp5x_base;
+	runtime->private_data = i2s_data;
+	return ret;
+}
+
+static int acp5x_dma_hw_params(struct snd_soc_component *component,
+			       struct snd_pcm_substream *substream,
+			       struct snd_pcm_hw_params *params)
+{
+	struct i2s_stream_instance *rtd;
+	struct snd_soc_pcm_runtime *prtd;
+	struct snd_soc_card *card;
+	struct acp5x_platform_info *pinfo;
+	struct i2s_dev_data *adata;
+	u64 size;
+
+	prtd = asoc_substream_to_rtd(substream);
+	card = prtd->card;
+	pinfo = snd_soc_card_get_drvdata(card);
+	adata = dev_get_drvdata(component->dev);
+	rtd = substream->runtime->private_data;
+
+	if (!rtd)
+		return -EINVAL;
+
+	if (pinfo) {
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			rtd->i2s_instance = pinfo->play_i2s_instance;
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				adata->play_stream = substream;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				adata->i2ssp_play_stream = substream;
+			}
+		} else {
+			rtd->i2s_instance = pinfo->cap_i2s_instance;
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				adata->capture_stream = substream;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				adata->i2ssp_capture_stream = substream;
+			}
+		}
+	} else {
+		pr_err("pinfo failed\n");
+	}
+	size = params_buffer_bytes(params);
+	rtd->dma_addr = substream->dma_buffer.addr;
+	rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
+	config_acp5x_dma(rtd, substream->stream);
+	return 0;
+}
+
+static snd_pcm_uframes_t acp5x_dma_pointer(struct snd_soc_component *component,
+					   struct snd_pcm_substream *substream)
+{
+	struct i2s_stream_instance *rtd;
+	u32 pos;
+	u32 buffersize;
+	u64 bytescount;
+
+	rtd = substream->runtime->private_data;
+	buffersize = frames_to_bytes(substream->runtime,
+				     substream->runtime->buffer_size);
+	bytescount = acp_get_byte_count(rtd, substream->stream);
+	if (bytescount > rtd->bytescount)
+		bytescount -= rtd->bytescount;
+	pos = do_div(bytescount, buffersize);
+	return bytes_to_frames(substream->runtime, pos);
+}
+
+static int acp5x_dma_new(struct snd_soc_component *component,
+			 struct snd_soc_pcm_runtime *rtd)
+{
+	struct device *parent = component->dev->parent;
+
+	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
+				       parent, MIN_BUFFER, MAX_BUFFER);
+	return 0;
+}
+
+static int acp5x_dma_mmap(struct snd_soc_component *component,
+			  struct snd_pcm_substream *substream,
+			  struct vm_area_struct *vma)
+{
+	return snd_pcm_lib_default_mmap(substream, vma);
+}
+
+static int acp5x_dma_close(struct snd_soc_component *component,
+			   struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *prtd;
+	struct i2s_dev_data *adata;
+	struct i2s_stream_instance *ins;
+
+	prtd = asoc_substream_to_rtd(substream);
+	component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+	adata = dev_get_drvdata(component->dev);
+	ins = substream->runtime->private_data;
+	if (!ins)
+		return -EINVAL;
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		switch (ins->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			adata->play_stream = NULL;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			adata->i2ssp_play_stream = NULL;
+		}
+	} else {
+		switch (ins->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			adata->capture_stream = NULL;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			adata->i2ssp_capture_stream = NULL;
+		}
+	}
+	kfree(ins);
+	return 0;
+}
+
+static const struct snd_soc_component_driver acp5x_i2s_component = {
+	.name		= DRV_NAME,
+	.open		= acp5x_dma_open,
+	.close		= acp5x_dma_close,
+	.hw_params	= acp5x_dma_hw_params,
+	.pointer	= acp5x_dma_pointer,
+	.mmap		= acp5x_dma_mmap,
+	.pcm_construct	= acp5x_dma_new,
+};
+
 static int acp5x_audio_probe(struct platform_device *pdev)
 {
 	struct resource *res;
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 44662e54bd34..99298a2f38ce 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -6,6 +6,7 @@
  */
 
 #include "vg_chip_offset_byte.h"
+#include <sound/pcm.h>
 
 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
 #define ACP_DEVICE_ID 0x15E2
@@ -36,6 +37,39 @@
 #define	HS_TX_THRESHOLD 24
 #define	HS_RX_THRESHOLD 23
 
+#define I2S_SP_INSTANCE                 0x01
+#define I2S_HS_INSTANCE                 0x02
+
+#define ACP_SRAM_PTE_OFFSET	0x02050000
+#define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
+#define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
+#define ACP_SRAM_HS_PB_PTE_OFFSET	0x200
+#define ACP_SRAM_HS_CP_PTE_OFFSET	0x300
+#define PAGE_SIZE_4K_ENABLE 0x2
+#define I2S_SP_TX_MEM_WINDOW_START	0x4000000
+#define I2S_SP_RX_MEM_WINDOW_START	0x4020000
+#define I2S_HS_TX_MEM_WINDOW_START	0x4040000
+#define I2S_HS_RX_MEM_WINDOW_START	0x4060000
+
+#define SP_PB_FIFO_ADDR_OFFSET		0x500
+#define SP_CAPT_FIFO_ADDR_OFFSET	0x700
+#define HS_PB_FIFO_ADDR_OFFSET		0x900
+#define HS_CAPT_FIFO_ADDR_OFFSET	0xB00
+#define PLAYBACK_MIN_NUM_PERIODS    2
+#define PLAYBACK_MAX_NUM_PERIODS    8
+#define PLAYBACK_MAX_PERIOD_SIZE    8192
+#define PLAYBACK_MIN_PERIOD_SIZE    1024
+#define CAPTURE_MIN_NUM_PERIODS     2
+#define CAPTURE_MAX_NUM_PERIODS     8
+#define CAPTURE_MAX_PERIOD_SIZE     8192
+#define CAPTURE_MIN_PERIOD_SIZE     1024
+
+#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define MIN_BUFFER MAX_BUFFER
+#define FIFO_SIZE 0x100
+#define DMA_SIZE 0x40
+#define FRM_LEN 0x100
+
 struct i2s_dev_data {
 	unsigned int i2s_irq;
 	void __iomem *acp5x_base;
@@ -45,6 +79,31 @@ struct i2s_dev_data {
 	struct snd_pcm_substream *i2ssp_capture_stream;
 };
 
+struct i2s_stream_instance {
+	u16 num_pages;
+	u16 i2s_instance;
+	u16 direction;
+	u16 channels;
+	u32 xfer_resolution;
+	u32 val;
+	dma_addr_t dma_addr;
+	u64 bytescount;
+	void __iomem *acp5x_base;
+};
+
+union acp_dma_count {
+	struct {
+		u32 low;
+		u32 high;
+	} bcount;
+	u64 bytescount;
+};
+
+struct acp5x_platform_info {
+	u16 play_i2s_instance;
+	u16 cap_i2s_instance;
+};
+
 static inline u32 acp_readl(void __iomem *base_addr)
 {
 	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
@@ -54,3 +113,50 @@ static inline void acp_writel(u32 val, void __iomem *base_addr)
 {
 	writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
 }
+
+static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
+				     int direction)
+{
+	union acp_dma_count byte_count;
+
+	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			byte_count.bcount.high =
+				acp_readl(rtd->acp5x_base +
+					  ACP_HS_TX_LINEARPOSCNTR_HIGH);
+			byte_count.bcount.low =
+				acp_readl(rtd->acp5x_base +
+					  ACP_HS_TX_LINEARPOSCNTR_LOW);
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			byte_count.bcount.high =
+				acp_readl(rtd->acp5x_base +
+					  ACP_I2S_TX_LINEARPOSCNTR_HIGH);
+			byte_count.bcount.low =
+				acp_readl(rtd->acp5x_base +
+					  ACP_I2S_TX_LINEARPOSCNTR_LOW);
+		}
+	} else {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			byte_count.bcount.high =
+				acp_readl(rtd->acp5x_base +
+					  ACP_HS_RX_LINEARPOSCNTR_HIGH);
+			byte_count.bcount.low =
+				acp_readl(rtd->acp5x_base +
+					  ACP_HS_RX_LINEARPOSCNTR_LOW);
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			byte_count.bcount.high =
+				acp_readl(rtd->acp5x_base +
+					  ACP_I2S_RX_LINEARPOSCNTR_HIGH);
+			byte_count.bcount.low =
+				acp_readl(rtd->acp5x_base +
+					  ACP_I2S_RX_LINEARPOSCNTR_LOW);
+		}
+	}
+	return byte_count.bytescount;
+}
-- 
2.17.1

Re: [PATCH 07/12] ASoC: amd: add ACP5x pcm dma driver ops

[Pierre-Louis Bossart]

On 7/7/21 12:56 AM, Vijendar Mukunda wrote:
> This patch adds ACP5x PCM driver DMA operations.
> 
> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
> ---
>  sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
>  sound/soc/amd/vangogh/acp5x.h         | 106 +++++++++
>  2 files changed, 410 insertions(+), 2 deletions(-)
> 
> diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> index d79712587d30..a4235cf33548 100644
> --- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> +++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
> @@ -17,8 +17,42 @@
>  
>  #define DRV_NAME "acp5x_i2s_dma"
>  
> -static const struct snd_soc_component_driver acp5x_i2s_component = {
> -	.name		= DRV_NAME,
> +static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
> +	.info = SNDRV_PCM_INFO_INTERLEAVED |
> +		SNDRV_PCM_INFO_BLOCK_TRANSFER |
> +		SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
> +		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
> +	.formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |
> +		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,

is S24_4LE supported? seems more useful than 8-bit audio these days, no?

> +static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
> +{
> +	u16 page_idx;
> +	u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
> +	u32 reg_dma_size, reg_fifo_size;
> +	dma_addr_t addr;
> +
> +	addr = rtd->dma_addr;
> +	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
> +		switch (rtd->i2s_instance) {
> +		case I2S_HS_INSTANCE:
> +			val = ACP_SRAM_HS_PB_PTE_OFFSET;
> +			break;
> +		case I2S_SP_INSTANCE:
> +		default:
> +			val = ACP_SRAM_SP_PB_PTE_OFFSET;
> +		}
> +	} else {
> +		switch (rtd->i2s_instance) {
> +		case I2S_HS_INSTANCE:
> +			val = ACP_SRAM_HS_CP_PTE_OFFSET;
> +			break;
> +		case I2S_SP_INSTANCE:
> +		default:
> +			val = ACP_SRAM_SP_CP_PTE_OFFSET;
> +		}
> +	}
> +	/* Group Enable */
> +	acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
> +		   ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
> +	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
> +		   ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
> +
> +	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
> +		/* Load the low address of page int ACP SRAM through SRBM */
> +		low = lower_32_bits(addr);
> +		high = upper_32_bits(addr);
> +
> +		acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
> +		high |= BIT(31);
> +		acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
> +			   + 4);

use single line? I find the indentation style quite an eyesore...


> +		/* Move to next physically contiguous page */
> +		val += 8;
> +		addr += PAGE_SIZE;
> +	}
> +
> +	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
> +		switch (rtd->i2s_instance) {
> +		case I2S_HS_INSTANCE:
> +			reg_dma_size = ACP_HS_TX_DMA_SIZE;
> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> +					HS_PB_FIFO_ADDR_OFFSET;
> +			reg_fifo_addr = ACP_HS_TX_FIFOADDR;
> +			reg_fifo_size = ACP_HS_TX_FIFOSIZE;
> +			acp_writel(I2S_HS_TX_MEM_WINDOW_START,
> +				   rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
> +			break;
> +
> +		case I2S_SP_INSTANCE:
> +		default:
> +			reg_dma_size = ACP_I2S_TX_DMA_SIZE;
> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> +					SP_PB_FIFO_ADDR_OFFSET;
> +			reg_fifo_addr =	ACP_I2S_TX_FIFOADDR;
> +			reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
> +			acp_writel(I2S_SP_TX_MEM_WINDOW_START,
> +				   rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
> +		}
> +	} else {
> +		switch (rtd->i2s_instance) {
> +		case I2S_HS_INSTANCE:
> +			reg_dma_size = ACP_HS_RX_DMA_SIZE;
> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> +					HS_CAPT_FIFO_ADDR_OFFSET;
> +			reg_fifo_addr = ACP_HS_RX_FIFOADDR;
> +			reg_fifo_size = ACP_HS_RX_FIFOSIZE;
> +			acp_writel(I2S_HS_RX_MEM_WINDOW_START,
> +				   rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
> +			break;
> +
> +		case I2S_SP_INSTANCE:
> +		default:
> +			reg_dma_size = ACP_I2S_RX_DMA_SIZE;
> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
> +					SP_CAPT_FIFO_ADDR_OFFSET;
> +			reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
> +			reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
> +			acp_writel(I2S_SP_RX_MEM_WINDOW_START,
> +				   rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
> +		}
> +	}
> +	acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
> +	acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
> +	acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
> +	acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
> +		   | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
> +		   rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
> +}
> +

> +static int acp5x_dma_hw_params(struct snd_soc_component *component,
> +			       struct snd_pcm_substream *substream,
> +			       struct snd_pcm_hw_params *params)
> +{
> +	struct i2s_stream_instance *rtd;
> +	struct snd_soc_pcm_runtime *prtd;
> +	struct snd_soc_card *card;
> +	struct acp5x_platform_info *pinfo;
> +	struct i2s_dev_data *adata;
> +	u64 size;
> +
> +	prtd = asoc_substream_to_rtd(substream);
> +	card = prtd->card;
> +	pinfo = snd_soc_card_get_drvdata(card);
> +	adata = dev_get_drvdata(component->dev);
> +	rtd = substream->runtime->private_data;
> +
> +	if (!rtd)
> +		return -EINVAL;
> +
> +	if (pinfo) {
> +		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> +			rtd->i2s_instance = pinfo->play_i2s_instance;
> +			switch (rtd->i2s_instance) {
> +			case I2S_HS_INSTANCE:
> +				adata->play_stream = substream;
> +				break;
> +			case I2S_SP_INSTANCE:
> +			default:
> +				adata->i2ssp_play_stream = substream;
> +			}
> +		} else {
> +			rtd->i2s_instance = pinfo->cap_i2s_instance;
> +			switch (rtd->i2s_instance) {
> +			case I2S_HS_INSTANCE:
> +				adata->capture_stream = substream;
> +				break;
> +			case I2S_SP_INSTANCE:
> +			default:
> +				adata->i2ssp_capture_stream = substream;
> +			}
> +		}
> +	} else {
> +		pr_err("pinfo failed\n");

that seems like a rather useless message. if you want a log at least use dev_err(component->dev

> +	}
> +	size = params_buffer_bytes(params);
> +	rtd->dma_addr = substream->dma_buffer.addr;
> +	rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
> +	config_acp5x_dma(rtd, substream->stream);
> +	return 0;
> +}
> +

Re: [PATCH 07/12] ASoC: amd: add ACP5x pcm dma driver ops

[Mukunda,Vijendar]

On 7/7/21 9:57 PM, Pierre-Louis Bossart wrote:
> 
> 
> On 7/7/21 12:56 AM, Vijendar Mukunda wrote:
>> This patch adds ACP5x PCM driver DMA operations.
>>
>> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
>> ---
>>  sound/soc/amd/vangogh/acp5x-pcm-dma.c | 306 +++++++++++++++++++++++++-
>>  sound/soc/amd/vangogh/acp5x.h         | 106 +++++++++
>>  2 files changed, 410 insertions(+), 2 deletions(-)
>>
>> diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> index d79712587d30..a4235cf33548 100644
>> --- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> +++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
>> @@ -17,8 +17,42 @@
>>  
>>  #define DRV_NAME "acp5x_i2s_dma"
>>  
>> -static const struct snd_soc_component_driver acp5x_i2s_component = {
>> -	.name		= DRV_NAME,
>> +static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
>> +	.info = SNDRV_PCM_INFO_INTERLEAVED |
>> +		SNDRV_PCM_INFO_BLOCK_TRANSFER |
>> +		SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
>> +		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
>> +	.formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |
>> +		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
> 
> is S24_4LE supported? seems more useful than 8-bit audio these days, no?
AMD I2S controller doesn't support S24_LE format.
> 
>> +static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
>> +{
>> +	u16 page_idx;
>> +	u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
>> +	u32 reg_dma_size, reg_fifo_size;
>> +	dma_addr_t addr;
>> +
>> +	addr = rtd->dma_addr;
>> +	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
>> +		switch (rtd->i2s_instance) {
>> +		case I2S_HS_INSTANCE:
>> +			val = ACP_SRAM_HS_PB_PTE_OFFSET;
>> +			break;
>> +		case I2S_SP_INSTANCE:
>> +		default:
>> +			val = ACP_SRAM_SP_PB_PTE_OFFSET;
>> +		}
>> +	} else {
>> +		switch (rtd->i2s_instance) {
>> +		case I2S_HS_INSTANCE:
>> +			val = ACP_SRAM_HS_CP_PTE_OFFSET;
>> +			break;
>> +		case I2S_SP_INSTANCE:
>> +		default:
>> +			val = ACP_SRAM_SP_CP_PTE_OFFSET;
>> +		}
>> +	}
>> +	/* Group Enable */
>> +	acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
>> +		   ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
>> +	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
>> +		   ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
>> +
>> +	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
>> +		/* Load the low address of page int ACP SRAM through SRBM */
>> +		low = lower_32_bits(addr);
>> +		high = upper_32_bits(addr);
>> +
>> +		acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
>> +		high |= BIT(31);
>> +		acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val
>> +			   + 4);
> 
> use single line? I find the indentation style quite an eyesore...
will fix the indentation style.
> 
> 
>> +		/* Move to next physically contiguous page */
>> +		val += 8;
>> +		addr += PAGE_SIZE;
>> +	}
>> +
>> +	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
>> +		switch (rtd->i2s_instance) {
>> +		case I2S_HS_INSTANCE:
>> +			reg_dma_size = ACP_HS_TX_DMA_SIZE;
>> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> +					HS_PB_FIFO_ADDR_OFFSET;
>> +			reg_fifo_addr = ACP_HS_TX_FIFOADDR;
>> +			reg_fifo_size = ACP_HS_TX_FIFOSIZE;
>> +			acp_writel(I2S_HS_TX_MEM_WINDOW_START,
>> +				   rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
>> +			break;
>> +
>> +		case I2S_SP_INSTANCE:
>> +		default:
>> +			reg_dma_size = ACP_I2S_TX_DMA_SIZE;
>> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> +					SP_PB_FIFO_ADDR_OFFSET;
>> +			reg_fifo_addr =	ACP_I2S_TX_FIFOADDR;
>> +			reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
>> +			acp_writel(I2S_SP_TX_MEM_WINDOW_START,
>> +				   rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
>> +		}
>> +	} else {
>> +		switch (rtd->i2s_instance) {
>> +		case I2S_HS_INSTANCE:
>> +			reg_dma_size = ACP_HS_RX_DMA_SIZE;
>> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> +					HS_CAPT_FIFO_ADDR_OFFSET;
>> +			reg_fifo_addr = ACP_HS_RX_FIFOADDR;
>> +			reg_fifo_size = ACP_HS_RX_FIFOSIZE;
>> +			acp_writel(I2S_HS_RX_MEM_WINDOW_START,
>> +				   rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
>> +			break;
>> +
>> +		case I2S_SP_INSTANCE:
>> +		default:
>> +			reg_dma_size = ACP_I2S_RX_DMA_SIZE;
>> +			acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
>> +					SP_CAPT_FIFO_ADDR_OFFSET;
>> +			reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
>> +			reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
>> +			acp_writel(I2S_SP_RX_MEM_WINDOW_START,
>> +				   rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
>> +		}
>> +	}
>> +	acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
>> +	acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
>> +	acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
>> +	acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
>> +		   | BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
>> +		   rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
>> +}
>> +
> 
>> +static int acp5x_dma_hw_params(struct snd_soc_component *component,
>> +			       struct snd_pcm_substream *substream,
>> +			       struct snd_pcm_hw_params *params)
>> +{
>> +	struct i2s_stream_instance *rtd;
>> +	struct snd_soc_pcm_runtime *prtd;
>> +	struct snd_soc_card *card;
>> +	struct acp5x_platform_info *pinfo;
>> +	struct i2s_dev_data *adata;
>> +	u64 size;
>> +
>> +	prtd = asoc_substream_to_rtd(substream);
>> +	card = prtd->card;
>> +	pinfo = snd_soc_card_get_drvdata(card);
>> +	adata = dev_get_drvdata(component->dev);
>> +	rtd = substream->runtime->private_data;
>> +
>> +	if (!rtd)
>> +		return -EINVAL;
>> +
>> +	if (pinfo) {
>> +		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
>> +			rtd->i2s_instance = pinfo->play_i2s_instance;
>> +			switch (rtd->i2s_instance) {
>> +			case I2S_HS_INSTANCE:
>> +				adata->play_stream = substream;
>> +				break;
>> +			case I2S_SP_INSTANCE:
>> +			default:
>> +				adata->i2ssp_play_stream = substream;
>> +			}
>> +		} else {
>> +			rtd->i2s_instance = pinfo->cap_i2s_instance;
>> +			switch (rtd->i2s_instance) {
>> +			case I2S_HS_INSTANCE:
>> +				adata->capture_stream = substream;
>> +				break;
>> +			case I2S_SP_INSTANCE:
>> +			default:
>> +				adata->i2ssp_capture_stream = substream;
>> +			}
>> +		}
>> +	} else {
>> +		pr_err("pinfo failed\n");
> 
> that seems like a rather useless message. if you want a log at least use dev_err(component->dev
will fix it and post the new version.
> 
>> +	}
>> +	size = params_buffer_bytes(params);
>> +	rtd->dma_addr = substream->dma_buffer.addr;
>> +	rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
>> +	config_acp5x_dma(rtd, substream->stream);
>> +	return 0;
>> +}
>> +

Re: [PATCH 07/12] ASoC: amd: add ACP5x pcm dma driver ops

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 470 bytes --]

On Wed, Jul 07, 2021 at 11:26:18AM +0530, Vijendar Mukunda wrote:

> +	/* Group Enable */
> +	acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
> +		   ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
> +	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
> +		   ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);

This isn't connected to the kernel page size is it?  If so we might've
configured to 16K or 64K, or possibly even some other options - I know
those two are out there in the wild.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 07/12] ASoC: amd: add ACP5x pcm dma driver ops

[Mukunda,Vijendar]

On 7/7/21 10:00 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:18AM +0530, Vijendar Mukunda wrote:
> 
>> +	/* Group Enable */
>> +	acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
>> +		   ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
>> +	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
>> +		   ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
> 
> This isn't connected to the kernel page size is it?  If so we might've
> configured to 16K or 64K, or possibly even some other options - I know
> those two are out there in the wild.
> 
No this is not connected to kernel page size. This is internal to ACP IP.

[PATCH 08/12] ASoC: amd: add vangogh i2s controller driver

[Vijendar Mukunda]

Add Vangogh I2S controller driver to support two I2S controller
instances.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-i2s.c | 97 +++++++++++++++++++++++++++++++
 sound/soc/amd/vangogh/acp5x.h     |  4 ++
 2 files changed, 101 insertions(+)
 create mode 100644 sound/soc/amd/vangogh/acp5x-i2s.c

diff --git a/sound/soc/amd/vangogh/acp5x-i2s.c b/sound/soc/amd/vangogh/acp5x-i2s.c
new file mode 100644
index 000000000000..0945c6452189
--- /dev/null
+++ b/sound/soc/amd/vangogh/acp5x-i2s.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// AMD ALSA SoC PCM Driver
+//
+// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+#include <linux/dma-mapping.h>
+
+#include "acp5x.h"
+
+#define DRV_NAME "acp5x_i2s_playcap"
+
+static const struct snd_soc_component_driver acp5x_dai_component = {
+	.name = "acp5x-i2s",
+};
+
+static struct snd_soc_dai_driver acp5x_i2s_dai = {
+	.playback = {
+		.rates = SNDRV_PCM_RATE_8000_96000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+			SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+		.channels_min = 2,
+		.channels_max = 2,
+		.rate_min = 8000,
+		.rate_max = 96000,
+	},
+	.capture = {
+		.rates = SNDRV_PCM_RATE_8000_96000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+			SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
+		.channels_min = 2,
+		.channels_max = 2,
+		.rate_min = 8000,
+		.rate_max = 96000,
+	},
+};
+
+static int acp5x_dai_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct i2s_dev_data *adata;
+	int ret;
+
+	adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
+			     GFP_KERNEL);
+	if (!adata)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
+		return -ENOMEM;
+	}
+	adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
+					 resource_size(res));
+	if (IS_ERR(adata->acp5x_base))
+		return PTR_ERR(adata->acp5x_base);
+
+	adata->master_mode = I2S_MASTER_MODE_ENABLE;
+	dev_set_drvdata(&pdev->dev, adata);
+	ret = devm_snd_soc_register_component(&pdev->dev,
+					      &acp5x_dai_component,
+					      &acp5x_i2s_dai, 1);
+	if (ret) {
+		dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int acp5x_dai_remove(struct platform_device *pdev)
+{
+	/* As we use devm_ memory alloc there is nothing TBD here */
+	return 0;
+}
+
+static struct platform_driver acp5x_dai_driver = {
+	.probe = acp5x_dai_probe,
+	.remove = acp5x_dai_remove,
+	.driver = {
+		.name = "acp5x_i2s_playcap",
+	},
+};
+
+module_platform_driver(acp5x_dai_driver);
+
+MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
+MODULE_DESCRIPTION("AMD ACP5.x CPU DAI Driver");
+MODULE_ALIAS("platform:" DRV_NAME);
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 99298a2f38ce..27cdd3b08701 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -70,7 +70,11 @@
 #define DMA_SIZE 0x40
 #define FRM_LEN 0x100
 
+#define I2S_MASTER_MODE_ENABLE 0x01
+#define I2S_MASTER_MODE_DISABLE 0x00
+
 struct i2s_dev_data {
+	bool master_mode;
 	unsigned int i2s_irq;
 	void __iomem *acp5x_base;
 	struct snd_pcm_substream *play_stream;
-- 
2.17.1

[PATCH 09/12] ASoC: amd: add vangogh i2s dai driver ops

[Vijendar Mukunda]

Add Vangogh i2s dai driver ops.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-i2s.c | 341 ++++++++++++++++++++++++++++++
 sound/soc/amd/vangogh/acp5x.h     |  22 ++
 2 files changed, 363 insertions(+)

diff --git a/sound/soc/amd/vangogh/acp5x-i2s.c b/sound/soc/amd/vangogh/acp5x-i2s.c
index 0945c6452189..8382db68e29e 100644
--- a/sound/soc/amd/vangogh/acp5x-i2s.c
+++ b/sound/soc/amd/vangogh/acp5x-i2s.c
@@ -17,6 +17,346 @@
 
 #define DRV_NAME "acp5x_i2s_playcap"
 
+static int acp5x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
+			     unsigned int fmt)
+{
+	struct i2s_dev_data *adata;
+	int mode;
+
+	adata = snd_soc_dai_get_drvdata(cpu_dai);
+	mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+	switch (mode) {
+	case SND_SOC_DAIFMT_I2S:
+		adata->tdm_mode = TDM_DISABLE;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		adata->tdm_mode = TDM_ENABLE;
+		break;
+	default:
+		return -EINVAL;
+	}
+	mode = fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	switch (mode) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		adata->master_mode = I2S_MASTER_MODE_ENABLE;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFM:
+		adata->master_mode = I2S_MASTER_MODE_DISABLE;
+		break;
+	}
+	return 0;
+}
+
+static int acp5x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
+				  u32 tx_mask, u32 rx_mask,
+				  int slots, int slot_width)
+{
+	struct i2s_dev_data *adata;
+	u32 frm_len;
+	u16 slot_len;
+
+	adata = snd_soc_dai_get_drvdata(cpu_dai);
+
+	/* These values are as per Hardware Spec */
+	switch (slot_width) {
+	case SLOT_WIDTH_8:
+		slot_len = 8;
+		break;
+	case SLOT_WIDTH_16:
+		slot_len = 16;
+		break;
+	case SLOT_WIDTH_24:
+		slot_len = 24;
+		break;
+	case SLOT_WIDTH_32:
+		slot_len = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+	frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
+	adata->tdm_fmt = frm_len;
+	return 0;
+}
+
+static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
+			      struct snd_pcm_hw_params *params,
+			      struct snd_soc_dai *dai)
+{
+	struct i2s_stream_instance *rtd;
+	struct snd_pcm_runtime *runtime;
+	struct snd_soc_pcm_runtime *prtd;
+	struct snd_soc_card *card;
+	struct acp5x_platform_info *pinfo;
+	struct i2s_dev_data *adata;
+	union acp_i2stdm_mstrclkgen mclkgen;
+
+	u32 val;
+	u32 reg_val, frmt_reg, master_reg;
+	u32 lrclk_div_val, bclk_div_val;
+
+	lrclk_div_val = 0;
+	bclk_div_val = 0;
+	runtime = substream->runtime;
+	prtd = asoc_substream_to_rtd(substream);
+	rtd = substream->runtime->private_data;
+	card = prtd->card;
+	adata = snd_soc_dai_get_drvdata(dai);
+	pinfo = snd_soc_card_get_drvdata(card);
+	if (pinfo) {
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			rtd->i2s_instance = pinfo->play_i2s_instance;
+		else
+			rtd->i2s_instance = pinfo->cap_i2s_instance;
+	}
+
+	/* These values are as per Hardware Spec */
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_U8:
+	case SNDRV_PCM_FORMAT_S8:
+		rtd->xfer_resolution = 0x0;
+		break;
+	case SNDRV_PCM_FORMAT_S16_LE:
+		rtd->xfer_resolution = 0x02;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		rtd->xfer_resolution = 0x04;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		rtd->xfer_resolution = 0x05;
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_val = ACP_HSTDM_ITER;
+			frmt_reg = ACP_HSTDM_TXFRMT;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			reg_val = ACP_I2STDM_ITER;
+			frmt_reg = ACP_I2STDM_TXFRMT;
+		}
+	} else {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_val = ACP_HSTDM_IRER;
+			frmt_reg = ACP_HSTDM_RXFRMT;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			reg_val = ACP_I2STDM_IRER;
+			frmt_reg = ACP_I2STDM_RXFRMT;
+		}
+	}
+	if (adata->tdm_mode) {
+		val = acp_readl(rtd->acp5x_base + reg_val);
+		acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
+		acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
+	}
+	val = acp_readl(rtd->acp5x_base + reg_val);
+	val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
+	val = val | (rtd->xfer_resolution  << 3);
+	acp_writel(val, rtd->acp5x_base + reg_val);
+
+	if (adata->master_mode) {
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			master_reg = ACP_I2STDM2_MSTRCLKGEN;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			master_reg = ACP_I2STDM0_MSTRCLKGEN;
+			break;
+		}
+		mclkgen.bits.i2stdm_master_mode = 0x1;
+		if (adata->tdm_mode)
+			mclkgen.bits.i2stdm_format_mode = 0x01;
+		else
+			mclkgen.bits.i2stdm_format_mode = 0x0;
+		switch (params_format(params)) {
+		case SNDRV_PCM_FORMAT_S16_LE:
+			switch (params_rate(params)) {
+			case 8000:
+				bclk_div_val = 768;
+				break;
+			case 16000:
+				bclk_div_val = 384;
+				break;
+			case 24000:
+				bclk_div_val = 256;
+				break;
+			case 32000:
+				bclk_div_val = 192;
+				break;
+			case 44100:
+			case 48000:
+				bclk_div_val = 128;
+				break;
+			case 88200:
+			case 96000:
+				bclk_div_val = 64;
+				break;
+			case 192000:
+				bclk_div_val = 32;
+				break;
+			default:
+				return -EINVAL;
+			}
+			lrclk_div_val = 32;
+			break;
+		case SNDRV_PCM_FORMAT_S32_LE:
+			switch (params_rate(params)) {
+			case 8000:
+				bclk_div_val = 384;
+				break;
+			case 16000:
+				bclk_div_val = 192;
+				break;
+			case 24000:
+				bclk_div_val = 128;
+				break;
+			case 32000:
+				bclk_div_val = 96;
+				break;
+			case 44100:
+			case 48000:
+				bclk_div_val = 64;
+				break;
+			case 88200:
+			case 96000:
+				bclk_div_val = 32;
+				break;
+			case 192000:
+				bclk_div_val = 16;
+				break;
+			default:
+				return -EINVAL;
+			}
+			lrclk_div_val = 64;
+			break;
+		default:
+			return -EINVAL;
+		}
+		mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
+		mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
+		acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
+	}
+	return 0;
+}
+
+static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
+			     int cmd, struct snd_soc_dai *dai)
+{
+	struct i2s_stream_instance *rtd;
+	u32 ret, val, period_bytes, reg_val, ier_val, water_val;
+	u32 buf_size, buf_reg;
+
+	rtd = substream->runtime->private_data;
+	period_bytes = frames_to_bytes(substream->runtime,
+				       substream->runtime->period_size);
+	buf_size = frames_to_bytes(substream->runtime,
+				   substream->runtime->buffer_size);
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		rtd->bytescount = acp_get_byte_count(rtd,
+						     substream->stream);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				water_val =
+					ACP_HS_TX_INTR_WATERMARK_SIZE;
+				reg_val = ACP_HSTDM_ITER;
+				ier_val = ACP_HSTDM_IER;
+				buf_reg = ACP_HS_TX_RINGBUFSIZE;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				water_val =
+					ACP_I2S_TX_INTR_WATERMARK_SIZE;
+				reg_val = ACP_I2STDM_ITER;
+				ier_val = ACP_I2STDM_IER;
+				buf_reg = ACP_I2S_TX_RINGBUFSIZE;
+			}
+		} else {
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				water_val =
+					ACP_HS_RX_INTR_WATERMARK_SIZE;
+				reg_val = ACP_HSTDM_IRER;
+				ier_val = ACP_HSTDM_IER;
+				buf_reg = ACP_HS_RX_RINGBUFSIZE;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				water_val =
+					ACP_I2S_RX_INTR_WATERMARK_SIZE;
+				reg_val = ACP_I2STDM_IRER;
+				ier_val = ACP_I2STDM_IER;
+				buf_reg = ACP_I2S_RX_RINGBUFSIZE;
+			}
+		}
+		acp_writel(period_bytes, rtd->acp5x_base + water_val);
+		acp_writel(buf_size, rtd->acp5x_base + buf_reg);
+		val = acp_readl(rtd->acp5x_base + reg_val);
+		val = val | BIT(0);
+		acp_writel(val, rtd->acp5x_base + reg_val);
+		acp_writel(1, rtd->acp5x_base + ier_val);
+		ret = 0;
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				reg_val = ACP_HSTDM_ITER;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				reg_val = ACP_I2STDM_ITER;
+			}
+
+		} else {
+			switch (rtd->i2s_instance) {
+			case I2S_HS_INSTANCE:
+				reg_val = ACP_HSTDM_IRER;
+				break;
+			case I2S_SP_INSTANCE:
+			default:
+				reg_val = ACP_I2STDM_IRER;
+			}
+		}
+		val = acp_readl(rtd->acp5x_base + reg_val);
+		val = val & ~BIT(0);
+		acp_writel(val, rtd->acp5x_base + reg_val);
+
+		if (!(acp_readl(rtd->acp5x_base + ACP_HSTDM_ITER) & BIT(0)) &&
+		    !(acp_readl(rtd->acp5x_base + ACP_HSTDM_IRER) & BIT(0)))
+			acp_writel(0, rtd->acp5x_base + ACP_HSTDM_IER);
+		if (!(acp_readl(rtd->acp5x_base + ACP_I2STDM_ITER) & BIT(0)) &&
+		    !(acp_readl(rtd->acp5x_base + ACP_I2STDM_IRER) & BIT(0)))
+			acp_writel(0, rtd->acp5x_base + ACP_I2STDM_IER);
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static struct snd_soc_dai_ops acp5x_i2s_dai_ops = {
+	.hw_params = acp5x_i2s_hwparams,
+	.trigger = acp5x_i2s_trigger,
+	.set_fmt = acp5x_i2s_set_fmt,
+	.set_tdm_slot = acp5x_i2s_set_tdm_slot,
+};
+
 static const struct snd_soc_component_driver acp5x_dai_component = {
 	.name = "acp5x-i2s",
 };
@@ -40,6 +380,7 @@ static struct snd_soc_dai_driver acp5x_i2s_dai = {
 		.rate_min = 8000,
 		.rate_max = 96000,
 	},
+	.ops = &acp5x_i2s_dai_ops,
 };
 
 static int acp5x_dai_probe(struct platform_device *pdev)
diff --git a/sound/soc/amd/vangogh/acp5x.h b/sound/soc/amd/vangogh/acp5x.h
index 27cdd3b08701..bc4180f0bcfc 100644
--- a/sound/soc/amd/vangogh/acp5x.h
+++ b/sound/soc/amd/vangogh/acp5x.h
@@ -73,9 +73,20 @@
 #define I2S_MASTER_MODE_ENABLE 0x01
 #define I2S_MASTER_MODE_DISABLE 0x00
 
+#define SLOT_WIDTH_8 0x08
+#define SLOT_WIDTH_16 0x10
+#define SLOT_WIDTH_24 0x18
+#define SLOT_WIDTH_32 0x20
+#define TDM_ENABLE 1
+#define TDM_DISABLE 0
+#define ACP5x_ITER_IRER_SAMP_LEN_MASK	0x38
+
 struct i2s_dev_data {
+	bool tdm_mode;
 	bool master_mode;
 	unsigned int i2s_irq;
+	u16 i2s_instance;
+	u32 tdm_fmt;
 	void __iomem *acp5x_base;
 	struct snd_pcm_substream *play_stream;
 	struct snd_pcm_substream *capture_stream;
@@ -108,6 +119,17 @@ struct acp5x_platform_info {
 	u16 cap_i2s_instance;
 };
 
+union acp_i2stdm_mstrclkgen {
+	struct {
+		u32 i2stdm_master_mode : 1;
+		u32 i2stdm_format_mode : 1;
+		u32 i2stdm_lrclk_div_val : 9;
+		u32 i2stdm_bclk_div_val : 11;
+		u32:10;
+	} bitfields, bits;
+	u32  u32_all;
+};
+
 static inline u32 acp_readl(void __iomem *base_addr)
 {
 	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
-- 
2.17.1

Re: [PATCH 09/12] ASoC: amd: add vangogh i2s dai driver ops

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 584 bytes --]

On Wed, Jul 07, 2021 at 11:26:20AM +0530, Vijendar Mukunda wrote:

> +	mode = fmt & SND_SOC_DAIFMT_MASTER_MASK;
> +	switch (mode) {
> +	case SND_SOC_DAIFMT_CBS_CFS:
> +		adata->master_mode = I2S_MASTER_MODE_ENABLE;
> +		break;
> +	case SND_SOC_DAIFMT_CBM_CFM:
> +		adata->master_mode = I2S_MASTER_MODE_DISABLE;
> +		break;
> +	}

As part of moving to more modern terminology it'd be good to move to
_DAIFMT_CLOCK_PROVIDER_MASK and associated constants (with a similar
change for the driver local constant) - see f026c12300 (ASoC: topology:
use inclusive language for bclk and fsync).

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 09/12] ASoC: amd: add vangogh i2s dai driver ops

[Mukunda,Vijendar]

On 7/7/21 10:05 PM, Mark Brown wrote:
> On Wed, Jul 07, 2021 at 11:26:20AM +0530, Vijendar Mukunda wrote:
> 
>> +	mode = fmt & SND_SOC_DAIFMT_MASTER_MASK;
>> +	switch (mode) {
>> +	case SND_SOC_DAIFMT_CBS_CFS:
>> +		adata->master_mode = I2S_MASTER_MODE_ENABLE;
>> +		break;
>> +	case SND_SOC_DAIFMT_CBM_CFM:
>> +		adata->master_mode = I2S_MASTER_MODE_DISABLE;
>> +		break;
>> +	}
> 
> As part of moving to more modern terminology it'd be good to move to
> _DAIFMT_CLOCK_PROVIDER_MASK and associated constants (with a similar
> change for the driver local constant) - see f026c12300 (ASoC: topology:
> use inclusive language for bclk and fsync).
> 

We will modify the code and will post the new version.

[PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Vijendar Mukunda]

Add Vangogh acp pci driver pm ops.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/pci-acp5x.c | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/sound/soc/amd/vangogh/pci-acp5x.c b/sound/soc/amd/vangogh/pci-acp5x.c
index 2779423f7cd3..c95e2212188f 100644
--- a/sound/soc/amd/vangogh/pci-acp5x.c
+++ b/sound/soc/amd/vangogh/pci-acp5x.c
@@ -10,6 +10,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
 
 #include "acp5x.h"
 
@@ -255,6 +256,10 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 	default:
 		dev_info(&pci->dev, "ACP audio mode : %d\n", val);
 	}
+	pm_runtime_set_autosuspend_delay(&pci->dev, 2000);
+	pm_runtime_use_autosuspend(&pci->dev);
+	pm_runtime_put_noidle(&pci->dev);
+	pm_runtime_allow(&pci->dev);
 	return 0;
 
 unregister_devs:
@@ -272,6 +277,41 @@ static int snd_acp5x_probe(struct pci_dev *pci,
 	return ret;
 }
 
+static int snd_acp5x_suspend(struct device *dev)
+{
+	int ret;
+	struct acp5x_dev_data *adata;
+
+	adata = dev_get_drvdata(dev);
+	ret = acp5x_deinit(adata->acp5x_base);
+	if (ret)
+		dev_err(dev, "ACP de-init failed\n");
+	else
+		dev_dbg(dev, "ACP de-initialized\n");
+
+	return ret;
+}
+
+static int snd_acp5x_resume(struct device *dev)
+{
+	int ret;
+	struct acp5x_dev_data *adata;
+
+	adata = dev_get_drvdata(dev);
+	ret = acp5x_init(adata->acp5x_base);
+	if (ret) {
+		dev_err(dev, "ACP init failed\n");
+		return ret;
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops acp5x_pm = {
+	.runtime_suspend = snd_acp5x_suspend,
+	.runtime_resume =  snd_acp5x_resume,
+	.resume =	snd_acp5x_resume,
+};
+
 static void snd_acp5x_remove(struct pci_dev *pci)
 {
 	struct acp5x_dev_data *adata;
@@ -285,6 +325,8 @@ static void snd_acp5x_remove(struct pci_dev *pci)
 	ret = acp5x_deinit(adata->acp5x_base);
 	if (ret)
 		dev_err(&pci->dev, "ACP de-init failed\n");
+	pm_runtime_forbid(&pci->dev);
+	pm_runtime_get_noresume(&pci->dev);
 	pci_release_regions(pci);
 	pci_disable_device(pci);
 }
@@ -302,6 +344,9 @@ static struct pci_driver acp5x_driver  = {
 	.id_table = snd_acp5x_ids,
 	.probe = snd_acp5x_probe,
 	.remove = snd_acp5x_remove,
+	.driver = {
+		.pm = &acp5x_pm,
+	}
 };
 
 module_pci_driver(acp5x_driver);
-- 
2.17.1

Re: [PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Pierre-Louis Bossart]

> +static int snd_acp5x_suspend(struct device *dev)
> +{
> +	int ret;
> +	struct acp5x_dev_data *adata;
> +
> +	adata = dev_get_drvdata(dev);
> +	ret = acp5x_deinit(adata->acp5x_base);
> +	if (ret)
> +		dev_err(dev, "ACP de-init failed\n");
> +	else
> +		dev_dbg(dev, "ACP de-initialized\n");
> +
> +	return ret;
> +}
> +
> +static int snd_acp5x_resume(struct device *dev)
> +{
> +	int ret;
> +	struct acp5x_dev_data *adata;
> +
> +	adata = dev_get_drvdata(dev);
> +	ret = acp5x_init(adata->acp5x_base);
> +	if (ret) {
> +		dev_err(dev, "ACP init failed\n");
> +		return ret;
> +	}
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops acp5x_pm = {
> +	.runtime_suspend = snd_acp5x_suspend,
> +	.runtime_resume =  snd_acp5x_resume,
> +	.resume =	snd_acp5x_resume,

use SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS?

also not clear why you don't have a .suspend here?

And to avoid warnings use __maybe_unused for those callbacks when PM is disabled?

Re: [PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Mukunda,Vijendar]

On 7/7/21 10:04 PM, Pierre-Louis Bossart wrote:
> 
>> +static int snd_acp5x_suspend(struct device *dev)
>> +{
>> +	int ret;
>> +	struct acp5x_dev_data *adata;
>> +
>> +	adata = dev_get_drvdata(dev);
>> +	ret = acp5x_deinit(adata->acp5x_base);
>> +	if (ret)
>> +		dev_err(dev, "ACP de-init failed\n");
>> +	else
>> +		dev_dbg(dev, "ACP de-initialized\n");
>> +
>> +	return ret;
>> +}
>> +
>> +static int snd_acp5x_resume(struct device *dev)
>> +{
>> +	int ret;
>> +	struct acp5x_dev_data *adata;
>> +
>> +	adata = dev_get_drvdata(dev);
>> +	ret = acp5x_init(adata->acp5x_base);
>> +	if (ret) {
>> +		dev_err(dev, "ACP init failed\n");
>> +		return ret;
>> +	}
>> +	return 0;
>> +}
>> +
>> +static const struct dev_pm_ops acp5x_pm = {
>> +	.runtime_suspend = snd_acp5x_suspend,
>> +	.runtime_resume =  snd_acp5x_resume,
>> +	.resume =	snd_acp5x_resume,
> 
> use SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS?

 We will modify the code.
> 
> also not clear why you don't have a .suspend here
It was a miss. we will add .suspend callback which invokes same callback
"snd_acp5x_suspend".
> 
> And to avoid warnings use __maybe_unused for those callbacks when PM is disabled?
> 
Agreed. We will modify the code and post the new version.
> 

Re: [PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Mukunda,Vijendar]

On 7/8/21 5:11 PM, Mukunda,Vijendar wrote:
> On 7/7/21 10:04 PM, Pierre-Louis Bossart wrote:
>>
>>> +static int snd_acp5x_suspend(struct device *dev)
>>> +{
>>> +	int ret;
>>> +	struct acp5x_dev_data *adata;
>>> +
>>> +	adata = dev_get_drvdata(dev);
>>> +	ret = acp5x_deinit(adata->acp5x_base);
>>> +	if (ret)
>>> +		dev_err(dev, "ACP de-init failed\n");
>>> +	else
>>> +		dev_dbg(dev, "ACP de-initialized\n");
>>> +
>>> +	return ret;
>>> +}
>>> +
>>> +static int snd_acp5x_resume(struct device *dev)
>>> +{
>>> +	int ret;
>>> +	struct acp5x_dev_data *adata;
>>> +
>>> +	adata = dev_get_drvdata(dev);
>>> +	ret = acp5x_init(adata->acp5x_base);
>>> +	if (ret) {
>>> +		dev_err(dev, "ACP init failed\n");
>>> +		return ret;
>>> +	}
>>> +	return 0;
>>> +}
>>> +
>>> +static const struct dev_pm_ops acp5x_pm = {
>>> +	.runtime_suspend = snd_acp5x_suspend,
>>> +	.runtime_resume =  snd_acp5x_resume,
>>> +	.resume =	snd_acp5x_resume,
>>
>> use SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS?
> 
suspend and resume callbacks implementation is same for runtime pm ops
and system level pm ops in ACP PCI driver i.e in suspend callback acp
de-init sequence will be invoked and in resume callback acp init
sequence will be invoked.
As per our understanding if we safeguard code with CONFIG_PM_SLEEP
macro, then runtime pm ops won't work.

Do we need to duplicate the same code as mentioned below?

static const struct dev_pm_ops acp5x_pm = {
        SET_RUNTIME_PM_OPS(snd_acp5x_runtime_suspend,
                           snd_acp5x_runtime_resume, NULL)
        SET_SYSTEM_SLEEP_PM_OPS(snd_acp5x_suspend, snd_acp5x_resume)
};

where snd_acp5x_runtime_suspend() & snd_acp5x_suspend() API
implementation is same. Similarly snd_acp5x_runtime_resume() &
snd_acp5x_resume() implementation is same.
>  We will modify the code.
>>
>> also not clear why you don't have a .suspend here
> It was a miss. we will add .suspend callback which invokes same callback
> "snd_acp5x_suspend".
>>
>> And to avoid warnings use __maybe_unused for those callbacks when PM is disabled?
>>
> Agreed. We will modify the code and post the new version.
>>
> 

Re: [PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1268 bytes --]

On Tue, Jul 13, 2021 at 12:06:38PM +0530, Mukunda,Vijendar wrote:
> On 7/8/21 5:11 PM, Mukunda,Vijendar wrote:
> > On 7/7/21 10:04 PM, Pierre-Louis Bossart wrote:

> >>> +static const struct dev_pm_ops acp5x_pm = {
> >>> +	.runtime_suspend = snd_acp5x_suspend,
> >>> +	.runtime_resume =  snd_acp5x_resume,
> >>> +	.resume =	snd_acp5x_resume,

> >> use SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS?

> suspend and resume callbacks implementation is same for runtime pm ops
> and system level pm ops in ACP PCI driver i.e in suspend callback acp
> de-init sequence will be invoked and in resume callback acp init
> sequence will be invoked.

> As per our understanding if we safeguard code with CONFIG_PM_SLEEP
> macro, then runtime pm ops won't work.

That's not what Pierre is suggesting though?

> Do we need to duplicate the same code as mentioned below?

> static const struct dev_pm_ops acp5x_pm = {
>         SET_RUNTIME_PM_OPS(snd_acp5x_runtime_suspend,
>                            snd_acp5x_runtime_resume, NULL)
>         SET_SYSTEM_SLEEP_PM_OPS(snd_acp5x_suspend, snd_acp5x_resume)
> };

Using the SET_ macros doesn't require that you duplicate the functions,
it literally just means changing the way the ops are assigned.  

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 10/12] ASoC: amd: add vangogh pci driver pm ops

[Mukunda,Vijendar]

On 7/14/21 9:53 PM, Mark Brown wrote:
> On Tue, Jul 13, 2021 at 12:06:38PM +0530, Mukunda,Vijendar wrote:
>> On 7/8/21 5:11 PM, Mukunda,Vijendar wrote:
>>> On 7/7/21 10:04 PM, Pierre-Louis Bossart wrote:
> 
>>>>> +static const struct dev_pm_ops acp5x_pm = {
>>>>> +	.runtime_suspend = snd_acp5x_suspend,
>>>>> +	.runtime_resume =  snd_acp5x_resume,
>>>>> +	.resume =	snd_acp5x_resume,
> 
>>>> use SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS?
> 
>> suspend and resume callbacks implementation is same for runtime pm ops
>> and system level pm ops in ACP PCI driver i.e in suspend callback acp
>> de-init sequence will be invoked and in resume callback acp init
>> sequence will be invoked.
> 
>> As per our understanding if we safeguard code with CONFIG_PM_SLEEP
>> macro, then runtime pm ops won't work.
> 
> That's not what Pierre is suggesting though?
> 
>> Do we need to duplicate the same code as mentioned below?
> 
>> static const struct dev_pm_ops acp5x_pm = {
>>         SET_RUNTIME_PM_OPS(snd_acp5x_runtime_suspend,
>>                            snd_acp5x_runtime_resume, NULL)
>>         SET_SYSTEM_SLEEP_PM_OPS(snd_acp5x_suspend, snd_acp5x_resume)
>> };
> 
> Using the SET_ macros doesn't require that you duplicate the functions,
> it literally just means changing the way the ops are assigned.  
> 
 Will make the changes and post the new version.

[PATCH 11/12] ASoc: amd: add vangogh i2s dma driver pm ops

[Vijendar Mukunda]

Add Vangogh i2s dma driver pm ops

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/vangogh/acp5x-pcm-dma.c | 84 +++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/sound/soc/amd/vangogh/acp5x-pcm-dma.c b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
index a4235cf33548..c90d9620e977 100644
--- a/sound/soc/amd/vangogh/acp5x-pcm-dma.c
+++ b/sound/soc/amd/vangogh/acp5x-pcm-dma.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/pm_runtime.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
@@ -419,19 +420,102 @@ static int acp5x_audio_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "ACP5x I2S IRQ request failed\n");
 		return -ENODEV;
 	}
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_allow(&pdev->dev);
 	return 0;
 }
 
 static int acp5x_audio_remove(struct platform_device *pdev)
 {
+	pm_runtime_disable(&pdev->dev);
 	return 0;
 }
 
+static int acp5x_resume(struct device *dev)
+{
+	struct i2s_dev_data *adata;
+	u32 val, reg_val, frmt_val;
+
+	reg_val = 0;
+	frmt_val = 0;
+	adata = dev_get_drvdata(dev);
+
+	if (adata->play_stream && adata->play_stream->runtime) {
+		struct i2s_stream_instance *rtd =
+			adata->play_stream->runtime->private_data;
+		config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_val = ACP_HSTDM_ITER;
+			frmt_val = ACP_HSTDM_TXFRMT;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			reg_val = ACP_I2STDM_ITER;
+			frmt_val = ACP_I2STDM_TXFRMT;
+		}
+		acp_writel((rtd->xfer_resolution  << 3),
+			   rtd->acp5x_base + reg_val);
+	}
+
+	if (adata->capture_stream && adata->capture_stream->runtime) {
+		struct i2s_stream_instance *rtd =
+			adata->capture_stream->runtime->private_data;
+		config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
+		switch (rtd->i2s_instance) {
+		case I2S_HS_INSTANCE:
+			reg_val = ACP_HSTDM_IRER;
+			frmt_val = ACP_HSTDM_RXFRMT;
+			break;
+		case I2S_SP_INSTANCE:
+		default:
+			reg_val = ACP_I2STDM_IRER;
+			frmt_val = ACP_I2STDM_RXFRMT;
+		}
+		acp_writel((rtd->xfer_resolution  << 3),
+			   rtd->acp5x_base + reg_val);
+	}
+	if (adata->tdm_mode == TDM_ENABLE) {
+		acp_writel(adata->tdm_fmt, adata->acp5x_base + frmt_val);
+		val = acp_readl(adata->acp5x_base + reg_val);
+		acp_writel(val | 0x2, adata->acp5x_base + reg_val);
+	}
+	acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
+	return 0;
+}
+
+static int acp5x_pcm_runtime_suspend(struct device *dev)
+{
+	struct i2s_dev_data *adata;
+
+	adata = dev_get_drvdata(dev);
+	acp_writel(0, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
+	return 0;
+}
+
+static int acp5x_pcm_runtime_resume(struct device *dev)
+{
+	struct i2s_dev_data *adata;
+
+	adata = dev_get_drvdata(dev);
+	acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
+	return 0;
+}
+
+static const struct dev_pm_ops acp5x_pm_ops = {
+	.runtime_suspend = acp5x_pcm_runtime_suspend,
+	.runtime_resume = acp5x_pcm_runtime_resume,
+	.resume = acp5x_resume,
+};
+
 static struct platform_driver acp5x_dma_driver = {
 	.probe = acp5x_audio_probe,
 	.remove = acp5x_audio_remove,
 	.driver = {
 		.name = "acp5x_i2s_dma",
+		.pm = &acp5x_pm_ops,
 	},
 };
 
-- 
2.17.1

[PATCH 12/12] ASoC: amd: enable vangogh acp5x driver build

[Vijendar Mukunda]

Vangogh ACP5x drivers can be built by selecting necessary
kernel config option.
The patch enables build support of the same.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/Kconfig          | 6 ++++++
 sound/soc/amd/Makefile         | 1 +
 sound/soc/amd/vangogh/Makefile | 9 +++++++++
 3 files changed, 16 insertions(+)
 create mode 100644 sound/soc/amd/vangogh/Makefile

diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig
index ba5a85bf7412..63e5b7549fb5 100644
--- a/sound/soc/amd/Kconfig
+++ b/sound/soc/amd/Kconfig
@@ -52,3 +52,9 @@ config SND_SOC_AMD_RENOIR_MACH
 	depends on SND_SOC_AMD_RENOIR
 	help
 	 This option enables machine driver for DMIC
+
+config SND_SOC_AMD_ACP5x
+	tristate "AMD Audio Coprocessor-v5.x I2S support"
+	depends on X86 && PCI
+	help
+	 This option enables ACP v5.x I2S support on AMD platform
diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile
index e6df2f72a2a1..07150d26f315 100644
--- a/sound/soc/amd/Makefile
+++ b/sound/soc/amd/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o
 obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/
 obj-$(CONFIG_SND_SOC_AMD_RV_RT5682_MACH) += snd-soc-acp-rt5682-mach.o
 obj-$(CONFIG_SND_SOC_AMD_RENOIR) += renoir/
+obj-$(CONFIG_SND_SOC_AMD_ACP5x) += vangogh/
diff --git a/sound/soc/amd/vangogh/Makefile b/sound/soc/amd/vangogh/Makefile
new file mode 100644
index 000000000000..3353f93dc610
--- /dev/null
+++ b/sound/soc/amd/vangogh/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Vangogh platform Support
+snd-pci-acp5x-objs	:= pci-acp5x.o
+snd-acp5x-i2s-objs	:= acp5x-i2s.o
+snd-acp5x-pcm-dma-objs	:= acp5x-pcm-dma.o
+
+obj-$(CONFIG_SND_SOC_AMD_ACP5x) += snd-pci-acp5x.o
+obj-$(CONFIG_SND_SOC_AMD_ACP5x)	+= snd-acp5x-i2s.o
+obj-$(CONFIG_SND_SOC_AMD_ACP5x) += snd-acp5x-pcm-dma.o
-- 
2.17.1

Re: [PATCH 12/12] ASoC: amd: enable vangogh acp5x driver build

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 13798 bytes --]

Hi Vijendar,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on asoc/for-next]
[also build test WARNING on v5.13 next-20210707]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Vijendar-Mukunda/Add-Vangogh-ACP-ASoC-driver/20210707-134319
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/a7ec99c34f0da98bd5a9b2ccbf7ed5ec7e4f06b2
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Vijendar-Mukunda/Add-Vangogh-ACP-ASoC-driver/20210707-134319
        git checkout a7ec99c34f0da98bd5a9b2ccbf7ed5ec7e4f06b2
        # save the attached .config to linux build tree
        make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   sound/soc/amd/vangogh/acp5x-i2s.c: In function 'acp5x_i2s_hwparams':
>> sound/soc/amd/vangogh/acp5x-i2s.c:87:26: warning: variable 'runtime' set but not used [-Wunused-but-set-variable]
      87 |  struct snd_pcm_runtime *runtime;
         |                          ^~~~~~~


vim +/runtime +87 sound/soc/amd/vangogh/acp5x-i2s.c

a404cc43cb3075 Vijendar Mukunda 2021-07-07   81  
a404cc43cb3075 Vijendar Mukunda 2021-07-07   82  static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
a404cc43cb3075 Vijendar Mukunda 2021-07-07   83  			      struct snd_pcm_hw_params *params,
a404cc43cb3075 Vijendar Mukunda 2021-07-07   84  			      struct snd_soc_dai *dai)
a404cc43cb3075 Vijendar Mukunda 2021-07-07   85  {
a404cc43cb3075 Vijendar Mukunda 2021-07-07   86  	struct i2s_stream_instance *rtd;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  @87  	struct snd_pcm_runtime *runtime;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   88  	struct snd_soc_pcm_runtime *prtd;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   89  	struct snd_soc_card *card;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   90  	struct acp5x_platform_info *pinfo;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   91  	struct i2s_dev_data *adata;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   92  	union acp_i2stdm_mstrclkgen mclkgen;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   93  
a404cc43cb3075 Vijendar Mukunda 2021-07-07   94  	u32 val;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   95  	u32 reg_val, frmt_reg, master_reg;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   96  	u32 lrclk_div_val, bclk_div_val;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   97  
a404cc43cb3075 Vijendar Mukunda 2021-07-07   98  	lrclk_div_val = 0;
a404cc43cb3075 Vijendar Mukunda 2021-07-07   99  	bclk_div_val = 0;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  100  	runtime = substream->runtime;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  101  	prtd = asoc_substream_to_rtd(substream);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  102  	rtd = substream->runtime->private_data;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  103  	card = prtd->card;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  104  	adata = snd_soc_dai_get_drvdata(dai);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  105  	pinfo = snd_soc_card_get_drvdata(card);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  106  	if (pinfo) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  107  		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
a404cc43cb3075 Vijendar Mukunda 2021-07-07  108  			rtd->i2s_instance = pinfo->play_i2s_instance;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  109  		else
a404cc43cb3075 Vijendar Mukunda 2021-07-07  110  			rtd->i2s_instance = pinfo->cap_i2s_instance;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  111  	}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  112  
a404cc43cb3075 Vijendar Mukunda 2021-07-07  113  	/* These values are as per Hardware Spec */
a404cc43cb3075 Vijendar Mukunda 2021-07-07  114  	switch (params_format(params)) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  115  	case SNDRV_PCM_FORMAT_U8:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  116  	case SNDRV_PCM_FORMAT_S8:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  117  		rtd->xfer_resolution = 0x0;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  118  		break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  119  	case SNDRV_PCM_FORMAT_S16_LE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  120  		rtd->xfer_resolution = 0x02;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  121  		break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  122  	case SNDRV_PCM_FORMAT_S24_LE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  123  		rtd->xfer_resolution = 0x04;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  124  		break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  125  	case SNDRV_PCM_FORMAT_S32_LE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  126  		rtd->xfer_resolution = 0x05;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  127  		break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  128  	default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  129  		return -EINVAL;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  130  	}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  131  	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  132  		switch (rtd->i2s_instance) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  133  		case I2S_HS_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  134  			reg_val = ACP_HSTDM_ITER;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  135  			frmt_reg = ACP_HSTDM_TXFRMT;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  136  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  137  		case I2S_SP_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  138  		default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  139  			reg_val = ACP_I2STDM_ITER;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  140  			frmt_reg = ACP_I2STDM_TXFRMT;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  141  		}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  142  	} else {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  143  		switch (rtd->i2s_instance) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  144  		case I2S_HS_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  145  			reg_val = ACP_HSTDM_IRER;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  146  			frmt_reg = ACP_HSTDM_RXFRMT;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  147  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  148  		case I2S_SP_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  149  		default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  150  			reg_val = ACP_I2STDM_IRER;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  151  			frmt_reg = ACP_I2STDM_RXFRMT;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  152  		}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  153  	}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  154  	if (adata->tdm_mode) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  155  		val = acp_readl(rtd->acp5x_base + reg_val);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  156  		acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  157  		acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  158  	}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  159  	val = acp_readl(rtd->acp5x_base + reg_val);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  160  	val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  161  	val = val | (rtd->xfer_resolution  << 3);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  162  	acp_writel(val, rtd->acp5x_base + reg_val);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  163  
a404cc43cb3075 Vijendar Mukunda 2021-07-07  164  	if (adata->master_mode) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  165  		switch (rtd->i2s_instance) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  166  		case I2S_HS_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  167  			master_reg = ACP_I2STDM2_MSTRCLKGEN;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  168  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  169  		case I2S_SP_INSTANCE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  170  		default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  171  			master_reg = ACP_I2STDM0_MSTRCLKGEN;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  172  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  173  		}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  174  		mclkgen.bits.i2stdm_master_mode = 0x1;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  175  		if (adata->tdm_mode)
a404cc43cb3075 Vijendar Mukunda 2021-07-07  176  			mclkgen.bits.i2stdm_format_mode = 0x01;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  177  		else
a404cc43cb3075 Vijendar Mukunda 2021-07-07  178  			mclkgen.bits.i2stdm_format_mode = 0x0;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  179  		switch (params_format(params)) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  180  		case SNDRV_PCM_FORMAT_S16_LE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  181  			switch (params_rate(params)) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  182  			case 8000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  183  				bclk_div_val = 768;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  184  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  185  			case 16000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  186  				bclk_div_val = 384;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  187  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  188  			case 24000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  189  				bclk_div_val = 256;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  190  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  191  			case 32000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  192  				bclk_div_val = 192;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  193  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  194  			case 44100:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  195  			case 48000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  196  				bclk_div_val = 128;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  197  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  198  			case 88200:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  199  			case 96000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  200  				bclk_div_val = 64;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  201  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  202  			case 192000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  203  				bclk_div_val = 32;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  204  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  205  			default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  206  				return -EINVAL;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  207  			}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  208  			lrclk_div_val = 32;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  209  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  210  		case SNDRV_PCM_FORMAT_S32_LE:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  211  			switch (params_rate(params)) {
a404cc43cb3075 Vijendar Mukunda 2021-07-07  212  			case 8000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  213  				bclk_div_val = 384;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  214  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  215  			case 16000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  216  				bclk_div_val = 192;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  217  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  218  			case 24000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  219  				bclk_div_val = 128;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  220  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  221  			case 32000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  222  				bclk_div_val = 96;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  223  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  224  			case 44100:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  225  			case 48000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  226  				bclk_div_val = 64;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  227  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  228  			case 88200:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  229  			case 96000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  230  				bclk_div_val = 32;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  231  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  232  			case 192000:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  233  				bclk_div_val = 16;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  234  				break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  235  			default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  236  				return -EINVAL;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  237  			}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  238  			lrclk_div_val = 64;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  239  			break;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  240  		default:
a404cc43cb3075 Vijendar Mukunda 2021-07-07  241  			return -EINVAL;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  242  		}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  243  		mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  244  		mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  245  		acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
a404cc43cb3075 Vijendar Mukunda 2021-07-07  246  	}
a404cc43cb3075 Vijendar Mukunda 2021-07-07  247  	return 0;
a404cc43cb3075 Vijendar Mukunda 2021-07-07  248  }
a404cc43cb3075 Vijendar Mukunda 2021-07-07  249  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65714 bytes --]

Re: [PATCH 12/12] ASoC: amd: enable vangogh acp5x driver build

[Mukunda,Vijendar]

On 7/7/21 2:30 PM, kernel test robot wrote:
> Hi Vijendar,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on asoc/for-next]
> [also build test WARNING on v5.13 next-20210707]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit-scm.com%2Fdocs%2Fgit-format-patch&data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=9vQMvlgt%2FiOFq%2FdI5VnTCSILABq3jF2TTn51bA6ZnhI%3D&reserved=0]
> 
> url:    https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommits%2FVijendar-Mukunda%2FAdd-Vangogh-ACP-ASoC-driver%2F20210707-134319&data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Fd10EeMdOg%2B3dgLGHsZWNTe%2FoAwLr8gL4vtl1nd0BeU%3D&reserved=0
> base:   https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbroonie%2Fsound.git&data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Siyl%2BraTkXA3xhX1IUBZjaJAopQIPdxAw4wpmUWYdxQ%3D&reserved=0 for-next
> config: x86_64-allyesconfig (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
> reproduce (this is a W=1 build):
>         # https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommit%2Fa7ec99c34f0da98bd5a9b2ccbf7ed5ec7e4f06b2&data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=lSqpjzxIP4OCK4Yrn4H5FsW4bR6msna%2F9Scpc8Y2310%3D&reserved=0
>         git remote add linux-review https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux&data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=AnV1Eu7Vd9mkjfIhSSgJiDu2%2Bcw5GlK%2B30tteeeHOPw%3D&reserved=0
>         git fetch --no-tags linux-review Vijendar-Mukunda/Add-Vangogh-ACP-ASoC-driver/20210707-134319
>         git checkout a7ec99c34f0da98bd5a9b2ccbf7ed5ec7e4f06b2
>         # save the attached .config to linux build tree
>         make W=1 ARCH=x86_64 
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    sound/soc/amd/vangogh/acp5x-i2s.c: In function 'acp5x_i2s_hwparams':
>>> sound/soc/amd/vangogh/acp5x-i2s.c:87:26: warning: variable 'runtime' set but not used [-Wunused-but-set-variable]
>       87 |  struct snd_pcm_runtime *runtime;
>          |                          ^~~~~~~
> 
will fix it and post the new version.
> 
> vim +/runtime +87 sound/soc/amd/vangogh/acp5x-i2s.c
> 
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   81  
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   82  static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   83  			      struct snd_pcm_hw_params *params,
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   84  			      struct snd_soc_dai *dai)
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   85  {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   86  	struct i2s_stream_instance *rtd;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  @87  	struct snd_pcm_runtime *runtime;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   88  	struct snd_soc_pcm_runtime *prtd;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   89  	struct snd_soc_card *card;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   90  	struct acp5x_platform_info *pinfo;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   91  	struct i2s_dev_data *adata;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   92  	union acp_i2stdm_mstrclkgen mclkgen;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   93  
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   94  	u32 val;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   95  	u32 reg_val, frmt_reg, master_reg;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   96  	u32 lrclk_div_val, bclk_div_val;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   97  
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   98  	lrclk_div_val = 0;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07   99  	bclk_div_val = 0;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  100  	runtime = substream->runtime;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  101  	prtd = asoc_substream_to_rtd(substream);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  102  	rtd = substream->runtime->private_data;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  103  	card = prtd->card;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  104  	adata = snd_soc_dai_get_drvdata(dai);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  105  	pinfo = snd_soc_card_get_drvdata(card);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  106  	if (pinfo) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  107  		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  108  			rtd->i2s_instance = pinfo->play_i2s_instance;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  109  		else
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  110  			rtd->i2s_instance = pinfo->cap_i2s_instance;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  111  	}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  112  
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  113  	/* These values are as per Hardware Spec */
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  114  	switch (params_format(params)) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  115  	case SNDRV_PCM_FORMAT_U8:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  116  	case SNDRV_PCM_FORMAT_S8:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  117  		rtd->xfer_resolution = 0x0;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  118  		break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  119  	case SNDRV_PCM_FORMAT_S16_LE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  120  		rtd->xfer_resolution = 0x02;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  121  		break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  122  	case SNDRV_PCM_FORMAT_S24_LE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  123  		rtd->xfer_resolution = 0x04;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  124  		break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  125  	case SNDRV_PCM_FORMAT_S32_LE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  126  		rtd->xfer_resolution = 0x05;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  127  		break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  128  	default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  129  		return -EINVAL;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  130  	}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  131  	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  132  		switch (rtd->i2s_instance) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  133  		case I2S_HS_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  134  			reg_val = ACP_HSTDM_ITER;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  135  			frmt_reg = ACP_HSTDM_TXFRMT;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  136  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  137  		case I2S_SP_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  138  		default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  139  			reg_val = ACP_I2STDM_ITER;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  140  			frmt_reg = ACP_I2STDM_TXFRMT;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  141  		}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  142  	} else {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  143  		switch (rtd->i2s_instance) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  144  		case I2S_HS_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  145  			reg_val = ACP_HSTDM_IRER;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  146  			frmt_reg = ACP_HSTDM_RXFRMT;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  147  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  148  		case I2S_SP_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  149  		default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  150  			reg_val = ACP_I2STDM_IRER;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  151  			frmt_reg = ACP_I2STDM_RXFRMT;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  152  		}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  153  	}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  154  	if (adata->tdm_mode) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  155  		val = acp_readl(rtd->acp5x_base + reg_val);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  156  		acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  157  		acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  158  	}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  159  	val = acp_readl(rtd->acp5x_base + reg_val);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  160  	val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  161  	val = val | (rtd->xfer_resolution  << 3);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  162  	acp_writel(val, rtd->acp5x_base + reg_val);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  163  
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  164  	if (adata->master_mode) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  165  		switch (rtd->i2s_instance) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  166  		case I2S_HS_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  167  			master_reg = ACP_I2STDM2_MSTRCLKGEN;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  168  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  169  		case I2S_SP_INSTANCE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  170  		default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  171  			master_reg = ACP_I2STDM0_MSTRCLKGEN;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  172  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  173  		}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  174  		mclkgen.bits.i2stdm_master_mode = 0x1;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  175  		if (adata->tdm_mode)
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  176  			mclkgen.bits.i2stdm_format_mode = 0x01;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  177  		else
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  178  			mclkgen.bits.i2stdm_format_mode = 0x0;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  179  		switch (params_format(params)) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  180  		case SNDRV_PCM_FORMAT_S16_LE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  181  			switch (params_rate(params)) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  182  			case 8000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  183  				bclk_div_val = 768;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  184  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  185  			case 16000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  186  				bclk_div_val = 384;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  187  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  188  			case 24000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  189  				bclk_div_val = 256;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  190  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  191  			case 32000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  192  				bclk_div_val = 192;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  193  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  194  			case 44100:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  195  			case 48000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  196  				bclk_div_val = 128;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  197  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  198  			case 88200:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  199  			case 96000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  200  				bclk_div_val = 64;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  201  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  202  			case 192000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  203  				bclk_div_val = 32;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  204  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  205  			default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  206  				return -EINVAL;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  207  			}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  208  			lrclk_div_val = 32;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  209  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  210  		case SNDRV_PCM_FORMAT_S32_LE:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  211  			switch (params_rate(params)) {
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  212  			case 8000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  213  				bclk_div_val = 384;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  214  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  215  			case 16000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  216  				bclk_div_val = 192;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  217  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  218  			case 24000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  219  				bclk_div_val = 128;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  220  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  221  			case 32000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  222  				bclk_div_val = 96;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  223  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  224  			case 44100:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  225  			case 48000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  226  				bclk_div_val = 64;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  227  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  228  			case 88200:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  229  			case 96000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  230  				bclk_div_val = 32;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  231  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  232  			case 192000:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  233  				bclk_div_val = 16;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  234  				break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  235  			default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  236  				return -EINVAL;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  237  			}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  238  			lrclk_div_val = 64;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  239  			break;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  240  		default:
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  241  			return -EINVAL;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  242  		}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  243  		mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  244  		mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  245  		acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  246  	}
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  247  	return 0;
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  248  }
> a404cc43cb3075 Vijendar Mukunda 2021-07-07  249  
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.01.org%2Fhyperkitty%2Flist%2Fkbuild-all%40lists.01.org&amp;data=04%7C01%7Cvijendar.mukunda%40amd.com%7C0f22ddb561f8401f59a408d94125bee3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637612455176116855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=F99HhZqgB7vMtLXCAYaWrWDGGDJPRPLaPKMJ%2FuKoa%2Bw%3D&amp;reserved=0
>