From: Yisheng Xie <xieyisheng1@huawei.com>
To: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Cc: <joro@8bytes.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>,
<lorenzo.pieralisi@arm.com>, <hanjun.guo@linaro.org>,
<sudeep.holla@arm.com>, <rjw@rjwysocki.net>, <lenb@kernel.org>,
<will.deacon@arm.com>, <robin.murphy@arm.com>,
<robert.moore@intel.com>, <lv.zheng@intel.com>,
<iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <devel@acpica.org>,
<liubo95@huawei.com>, <chenjiankang1@huawei.com>,
<xieyisheng@huawei.com>
Subject: Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3
Date: Wed, 6 Sep 2017 09:16:38 +0800 [thread overview]
Message-ID: <de1a6b52-5e4f-1c0a-af3d-f6adb4b01daf@huawei.com> (raw)
In-Reply-To: <95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>
Hi Jean-Philippe,
On 2017/9/5 20:56, Jean-Philippe Brucker wrote:
> On 31/08/17 09:20, Yisheng Xie wrote:
>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:
>> https://www.spinics.net/lists/arm-kernel/msg565155.html
>>
>> But for some platform devices(aka on-chip integrated devices), there is also
>> SVM requirement, which works based on the SMMU stall mode.
>> Jean-Philippe has prepared a prototype patchset to support it:
>> git://linux-arm.org/linux-jpb.git svm/stall
>
> Only meant for testing at that point, and unfit even for an RFC.
Sorry about that, I should ask you before send it out. It's my mistake. For I also
have some question about this patchset.
We have related device, and would like to do some help about it. Do you have
any plan about upstream ?
>
>> We tested this patchset with some fixes on a on-chip integrated device. The
>> basic function is ok, so I just send them out for review, although this
>> patchset heavily depends on the former patchset (PCIe SVM support for ARM
>> SMMUv3), which is still under discussion.
>>
>> Patch Overview:
>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits
>> *4 is to realise the SVM function for platform device
>> *5 is fix a bug when test SVM function while SMMU donnot support this feature
>> *6 avoid ILLEGAL setting of STE and CD entry about stall
>>
>> Acctually here, I also have some questions about SVM on SMMUv3:
>>
>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,
>> it will register a mmu_notify. Therefore, when a page range is invalid, we can
>> send TLBI or ATC invalid without BTM?
>
> We could, but the end goal for SVM is to perfectly mirror the CPU page
> tables. So for platform SVM we would like to get rid of MMU notifiers
> entirely.
I see, but for some SMMU which do not support BTM, it cannot benefit from SVM.
Meanwhile, do you mean even with BTM feature, the PCI-e device also need to send a
ATC invalid by MMU notify? It seems not fair, why not hardware do the entirely work
in this case? It may costly for send ATC invalid and sync.
>
>> 2. According to ACPI IORT spec, named component specific data has a node flags field
>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.
>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for
>> a single platform device which should be enough, because SMMU only support 20 bit pasid
>>
>> 3. Presently, the pasid is allocate for a task but not for a context, if a task is trying
>> to bind to 2 device A and B:
>> a) A support 5 pasid bits
>> b) B support 2 pasid bits
>> c) when the task bind to device A, it allocate pasid = 16
>> d) then it must be fail when trying to bind to task B, for its highest pasid is 4.
>> So it should allocate a single pasid for a context to avoid this?
>
> Ideally yes, but the model chosen for the IOMMU API was one PASID per
> task, so I implemented this model (the PASID allocator will be common to
> IOMMU core in the future).
It is fair, for each IOMMU need PASID allocator to support SVM.
Thanks
Yisheng Xie
>
> Therefore the PASID allocation will fail in your example, and there is no
> way around it. If you do (d) then (c), the task will have PASID 4.
>
> Thanks,
> Jean
>
> .
>
next prev parent reply other threads:[~2017-09-06 1:17 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-31 8:20 [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3 Yisheng Xie
2017-08-31 8:20 ` [RFC PATCH 1/6] dt-bindings: document stall and PASID properties for IOMMU masters Yisheng Xie
2017-09-05 12:52 ` Jean-Philippe Brucker
2017-08-31 8:20 ` [RFC PATCH 2/6] iommu/of: Add stall and pasid properties to iommu_fwspec Yisheng Xie
2017-09-05 12:52 ` Jean-Philippe Brucker
2017-08-31 8:20 ` [RFC PATCH 3/6] ACPI: IORT: " Yisheng Xie
2017-08-31 8:20 ` [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform devices Yisheng Xie
2017-09-05 12:53 ` Jean-Philippe Brucker
2017-09-06 0:51 ` Bob Liu
2017-09-06 1:20 ` Yisheng Xie
2017-08-31 8:20 ` [RFC PATCH 5/6] iommu/arm-smmu-v3: fix panic when handle stall mode irq Yisheng Xie
2017-09-05 12:53 ` Jean-Philippe Brucker
2017-08-31 8:20 ` [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S Yisheng Xie
2017-09-05 12:54 ` Jean-Philippe Brucker
2017-09-06 2:23 ` Yisheng Xie
2017-09-13 3:06 ` Will Deacon
2017-09-13 10:11 ` Yisheng Xie
2017-09-13 15:47 ` Jean-Philippe Brucker
2017-09-13 17:11 ` Will Deacon
2017-09-05 12:56 ` [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3 Jean-Philippe Brucker
2017-09-06 1:02 ` Bob Liu
2017-09-06 9:57 ` Jean-Philippe Brucker
2017-09-07 1:41 ` Bob Liu
2017-09-07 16:32 ` Jean-Philippe Brucker
2017-09-13 1:11 ` Bob Liu
2017-09-06 1:16 ` Yisheng Xie [this message]
2017-09-06 9:59 ` Jean-Philippe Brucker
2017-09-07 1:55 ` Bob Liu
2017-09-07 16:30 ` Jean-Philippe Brucker
2017-09-06 1:24 ` Hanjun Guo
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