Re: [PATCH] drm/msm/dp: remove limitation of link rate at 5.4G to support HBR3

[Kuogee Hsieh <quic_khsieh@quicinc.com>]

Hi Dmitry,


Link rate is advertised by sink, but adjusted (reduced the link rate)  
by host during link training.

Therefore should be fine if host did not support HBR3 rate.

It will reduce to lower link rate during link training procedures.

kuogee

On 10/31/2022 11:46 AM, Dmitry Baryshkov wrote:
> On 31/10/2022 20:27, Kuogee Hsieh wrote:
>> An HBR3-capable device shall also support TPS4. Since TPS4 feature
>> had been implemented already, it is not necessary to limit link
>> rate at HBR2 (5.4G). This patch remove this limitation to support
>> HBR3 (8.1G) link rate.
>
> The DP driver supports several platforms including sdm845 and can 
> support, if I'm not mistaken, platforms up to msm8998/sdm630/660. 
> Could you please confirm that all these SoCs have support for HBR3?
>
> With that fact being confirmed:
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
>
>>
>> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
>> ---
>>   drivers/gpu/drm/msm/dp/dp_panel.c | 4 ----
>>   1 file changed, 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c 
>> b/drivers/gpu/drm/msm/dp/dp_panel.c
>> index 5149ceb..3344f5a 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
>> @@ -78,10 +78,6 @@ static int dp_panel_read_dpcd(struct dp_panel 
>> *dp_panel)
>>       if (link_info->num_lanes > dp_panel->max_dp_lanes)
>>           link_info->num_lanes = dp_panel->max_dp_lanes;
>>   -    /* Limit support upto HBR2 until HBR3 support is added */
>> -    if (link_info->rate >= 
>> (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
>> -        link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
>> -
>>       drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
>>       drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
>>       drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", 
>> link_info->num_lanes);
>