From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17F8BC4320E for ; Wed, 28 Jul 2021 07:18:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00FF660F91 for ; Wed, 28 Jul 2021 07:18:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234990AbhG1HSA (ORCPT ); Wed, 28 Jul 2021 03:18:00 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:57659 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233225AbhG1HR5 (ORCPT ); Wed, 28 Jul 2021 03:17:57 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1627456676; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=uTWyTqMs+PRR6Vr7fo7QE9aqKJhA7o/4CIJbMLl7ewQ=; b=xaWwd00xOR3WTwy735j44Fh53J2EtW/ukWMLhy4lcoeg9waiPXDpw8P330wfMyjwI43TkB5z X6D7w8s/OVU4CPbq3TmVJSq8/SDK5kRgDEakZ//Mn25hpSmw8MblDtQLHevooNDE/4c8KON1 8oDdxvKt/iELyeWjSoyMwQ8BuKE= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 610104a24815712f3a159e6a (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 28 Jul 2021 07:17:53 GMT Sender: akhilpo=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 194B5C433F1; Wed, 28 Jul 2021 07:17:53 +0000 (UTC) Received: from [192.168.1.105] (unknown [59.89.229.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id F0052C433D3; Wed, 28 Jul 2021 07:17:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F0052C433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=akhilpo@codeaurora.org Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add gpu support To: Stephen Boyd , Bjorn Andersson , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS , Rob Herring , dri-devel@lists.freedesktop.org, freedreno , linux-arm-msm@vger.kernel.org Cc: Jonathan Marek , linux-kernel@vger.kernel.org, Douglas Anderson , Jordan Crouse , Andy Gross , Matthias Kaehlcke References: <1627147740-11590-1-git-send-email-akhilpo@codeaurora.org> From: Akhil P Oommen Message-ID: Date: Wed, 28 Jul 2021 12:47:45 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/27/2021 5:46 AM, Stephen Boyd wrote: > Quoting Akhil P Oommen (2021-07-24 10:29:00) >> Add the necessary dt nodes for gpu support in sc7280. >> >> Signed-off-by: Akhil P Oommen >> --- >> This patch has dependency on the GPUCC bindings patch here: >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-tdas@codeaurora.org/ > > To avoid the dependency the plain numbers can be used. But, won't that reduce readability and make things prone to error? If the other patch doesn't get picked up soon, we should try this option. We like to get this patch merged in v5.15. > >> >> Changes in v2: >> - formatting update and removed a duplicate header (Stephan) >> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 116 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 116 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 029723a..524a5e0 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -585,6 +586,121 @@ >> #clock-cells = <1>; >> }; >> >> + gpu@3d00000 { >> + compatible = "qcom,adreno-635.0", "qcom,adreno"; >> + #stream-id-cells = <16>; >> + reg = <0 0x03d00000 0 0x40000>, >> + <0 0x03d9e000 0 0x1000>, >> + <0 0x03d61000 0 0x800>; >> + reg-names = "kgsl_3d0_reg_memory", >> + "cx_mem", >> + "cx_dbgc"; >> + interrupts = ; >> + iommus = <&adreno_smmu 0 0x401>; >> + operating-points-v2 = <&gpu_opp_table>; >> + qcom,gmu = <&gmu>; >> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; >> + interconnect-names = "gfx-mem"; >> + >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-550000000 { >> + opp-hz = /bits/ 64 <550000000>; >> + opp-level = ; >> + opp-peak-kBps = <6832000>; >> + }; >> + >> + opp-450000000 { >> + opp-hz = /bits/ 64 <450000000>; >> + opp-level = ; >> + opp-peak-kBps = <4068000>; >> + }; >> + >> + opp-315000000 { >> + opp-hz = /bits/ 64 <315000000>; >> + opp-level = ; >> + opp-peak-kBps = <1804000>; >> + }; >> + }; >> + }; >> + >> + gmu: gmu@3d69000 { >> + compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; >> + reg = <0 0x03d6a000 0 0x34000>, >> + <0 0x3de0000 0 0x10000>, >> + <0 0x0b290000 0 0x10000>; >> + reg-names = "gmu", "rscc", "gmu_pdc"; >> + interrupts = , >> + ; >> + interrupt-names = "hfi", "gmu"; >> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_CXO_CLK>, >> + <&gcc GCC_DDRSS_GPU_AXI_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gpucc GPU_CC_AHB_CLK>, >> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; >> + clock-names = "gmu", >> + "cxo", >> + "axi", >> + "memnoc", >> + "ahb", >> + "hub", >> + "smmu_vote"; >> + power-domains = <&gpucc GPU_CC_CX_GDSC>, >> + <&gpucc GPU_CC_GX_GDSC>; >> + power-domain-names = "cx", >> + "gx"; >> + iommus = <&adreno_smmu 5 0x400>; >> + operating-points-v2 = <&gmu_opp_table>; >> + >> + gmu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>; >> + opp-level = ; >> + }; >> + }; >> + }; >> + >> + adreno_smmu: iommu@3da0000 { >> + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; >> + reg = <0 0x03da0000 0 0x20000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <2>; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + >> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >> + <&gpucc GPU_CC_AHB_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >> + <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >> + <&gpucc GPU_CC_HUB_AON_CLK>; >> + clock-names = "gcc_gpu_memnoc_gfx_clk", >> + "gcc_gpu_snoc_dvm_gfx_clk", >> + "gpu_cc_ahb_clk", >> + "gpu_cc_hlos1_vote_gpu_smmu_clk", >> + "gpu_cc_cx_gmu_clk", >> + "gpu_cc_hub_cx_int_clk", >> + "gpu_cc_hub_aon_clk"; >> + >> + power-domains = <&gpucc GPU_CC_CX_GDSC>; >> + }; >> + >> lpass_ag_noc: interconnect@3c40000 { > > This node is 3c40000 and the one above is 3da0000. 3c comes before 3d. > Please order nodes properly. Yeah, I messed up the order at a couple of places. Will fix. -Akhil. > >> reg = <0 0x03c40000 0 0xf080>; >> compatible = "qcom,sc7280-lpass-ag-noc";