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[46.138.117.53]) by smtp.googlemail.com with ESMTPSA id p8sm122711ljn.108.2021.08.11.18.40.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Aug 2021 18:40:06 -0700 (PDT) Subject: Re: [PATCH v7 02/37] soc/tegra: pmc: Implement attach_dev() of power domain drivers From: Dmitry Osipenko To: Ulf Hansson Cc: Thierry Reding , Jonathan Hunter , Viresh Kumar , Stephen Boyd , Peter De Schrijver , Linux Kernel Mailing List , linux-tegra , Linux PM References: <20210701232728.23591-1-digetx@gmail.com> <20210701232728.23591-3-digetx@gmail.com> <1034458d-78e0-5036-e278-6fee5d0d75ac@gmail.com> <6741262b-386b-7635-fd42-ebd4f877fddd@gmail.com> <8e110e08-1268-464c-6edb-0a3f640d43d6@gmail.com> Message-ID: Date: Thu, 12 Aug 2021 04:40:04 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <8e110e08-1268-464c-6edb-0a3f640d43d6@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 12.08.2021 01:41, Dmitry Osipenko пишет: >>> I am not saying you should change the clock rate. The current code >>> path that runs via devm_tegra_core_dev_init_opp_table() just calls >>> clk_get_rate and then dev_pm_opp_set_rate() with the current rate to >>> vote for the corresponding OPP level. Right? >>> >>> Isn't this exactly what you want? No? >> I see now what you meant, it's actually a simpler variant and it works >> too. Thank you for the suggestion, I'll prepare v8. >> > My bad, it doesn't work at all. I actually need to use the rpm_pstate or > something else because performance state is coupled with the enable > state of the device. If device is never rpm-suspended by consumer > driver, then the initialized performance state is never dropped. Hence I > want to initialize the state which is set only when device is resumed. > > I'll need to think more about it. GENPD core has these false assumptions: 1. It assumes that by default all devices are at zero performance level at a boot time. This is not true for Tegra because hardware is pre-initialized independently from GENPD. 2. It assumes that nothing depends on performance level and devices can operate at any level at any time. Not true for Tegra and other platforms where performance level is coupled with clocks state of attached devices. OPP framework glues clock and performance level together for us, which works good so far. Hence I either need to patch every driver to use dev_pm_opp_set_rate in order to sync clk rate with the perf level at device runtime, or I need to preset the rpm perf level to allow GENPD core to set the level before device is resumed.