From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E8D0C77B76 for ; Tue, 18 Apr 2023 01:53:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbjDRBxl (ORCPT ); Mon, 17 Apr 2023 21:53:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229687AbjDRBxj (ORCPT ); Mon, 17 Apr 2023 21:53:39 -0400 Received: from out199-18.us.a.mail.aliyun.com (out199-18.us.a.mail.aliyun.com [47.90.199.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA9ED420F; Mon, 17 Apr 2023 18:52:46 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R171e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=baolin.wang@linux.alibaba.com;NM=1;PH=DS;RN=12;SR=0;TI=SMTPD_---0VgN.twa_1681782660; Received: from 30.97.48.52(mailfrom:baolin.wang@linux.alibaba.com fp:SMTPD_---0VgN.twa_1681782660) by smtp.aliyun-inc.com; Tue, 18 Apr 2023 09:51:01 +0800 Message-ID: Date: Tue, 18 Apr 2023 09:51:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v2 2/3] drivers/perf: add DesignWare PCIe PMU driver To: Shuai Xue , helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, zhuo.song@linux.alibaba.com References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> <20230410031702.68355-3-xueshuai@linux.alibaba.com> <713d8162-dd3c-483c-b984-7707ef8aaa36@linux.alibaba.com> From: Baolin Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/17/2023 9:16 AM, Shuai Xue wrote: [snip] >>> + >>> +static void dwc_pcie_pmu_event_update(struct perf_event *event) >>> +{ >>> +    u64 counter; >>> +    struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu); >>> +    struct dwc_pcie_rp_info *rp_info = pmu_to_pcie_info(event->pmu); >>> +    struct pci_dev *pdev = rp_info->pdev; >>> +    u16 ras_des = rp_info->ras_des; >>> +    struct hw_perf_event *hwc = &event->hw; >>> +    enum dwc_pcie_event_type type = DWC_PCIE_EVENT_TYPE(event); >>> +    u64 delta, prev, now; >>> + >>> +    do { >>> +        prev = local64_read(&hwc->prev_count); >>> + >>> +        if (type == DWC_PCIE_LANE_EVENT) >>> +            dwc_pcie_pmu_read_event_counter(pdev, ras_des, &counter); >>> +        else if (type == DWC_PCIE_TIME_BASE_EVENT) >>> +            dwc_pcie_pmu_read_base_time_counter(pdev, ras_des, >>> +                                &counter); >>> +        else >>> +            dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); >>> + >>> +        now = counter; >>> +    } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); >>> + >>> +    delta = now - prev; >> >> This can be overflow? better to add a mask to avoid possible overflow. > > I think it can not. This Root Complex supports up to PCIe Gen5 (32 GT/s) > and one root port support up to x16 lanes, with peek bandwidth 64 GB/s. > On Yitian 710, one root port is x4 lane with peak bandwidth 16 GB/s. > The counter is 64 bit width with 16 bytes unit. > > 2^64*16/(64*10^9)/60/60/24/365 = 146 years > > For x16 root port, it will not overflow within 146 yeasr and for yitian 710, > it will never overflow in my life too. However the lane event counter is 32bit, so still a maximum counter mask is preferable.