From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B959DC433B4 for ; Thu, 29 Apr 2021 05:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 907D96144E for ; Thu, 29 Apr 2021 05:33:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236837AbhD2FeW (ORCPT ); Thu, 29 Apr 2021 01:34:22 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:34102 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbhD2FeU (ORCPT ); Thu, 29 Apr 2021 01:34:20 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1619674414; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=bsA0nxUjD3KYsDuCWjb6jWZWnBa2V9HdYdOfdgr6mLY=; b=HWR8K4TWI3Ctb9WoEGphVT0Y1EzJLfiH0XkZoov4VfO+CAuujkKviL4OhyQvaY21O2yD3Yyr EQafd5qsuPpE71tXmffICruFHBVe9utCCfxtlc1CQiRvq9MDC1iV7/UL7TqwGoNKsZiiEh6n Zu+pPCFEQg9A/y7L0yqTQNcEhmA= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 608a452de0e9c9a6b6864edf (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 29 Apr 2021 05:33:33 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BB093C433D3; Thu, 29 Apr 2021 05:33:33 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id E371DC4338A; Thu, 29 Apr 2021 05:33:32 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 29 Apr 2021 11:03:32 +0530 From: Sibi Sankar To: Philipp Zabel Cc: robh+dt@kernel.org, bjorn.andersson@linaro.org, sboyd@kernel.org, agross@kernel.org, mani@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/5] reset: qcom: Add PDC Global reset signals for WPSS In-Reply-To: <0c5f747fe0a3f757a4160e4fd28cc2b56a57a39d.camel@pengutronix.de> References: <1619508824-14413-1-git-send-email-sibis@codeaurora.org> <1619508824-14413-5-git-send-email-sibis@codeaurora.org> <0c5f747fe0a3f757a4160e4fd28cc2b56a57a39d.camel@pengutronix.de> Message-ID: X-Sender: sibis@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hey Philipp, Thanks for the review. Will get them fixed in the next re-spin. On 2021-04-27 13:28, Philipp Zabel wrote: > Hi Sibi, > > On Tue, 2021-04-27 at 13:03 +0530, Sibi Sankar wrote: >> Add PDC Global reset signals for Wireless Processor Subsystem (WPSS) >> on SC7280 SoCs. >> >> Signed-off-by: Sibi Sankar >> --- >> >> v2: >> * place resets and num_resets adjacent to each other [Stephen] > [...] >> +struct qcom_pdc_reset_desc { >> + const struct qcom_pdc_reset_map *resets; >> + size_t num_resets; >> + unsigned int offset; >> +}; > [...] > > For consistency, please do the same here: > >> +static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = { >> + .resets = sdm845_pdc_resets, >> + .offset = RPMH_SDM845_PDC_SYNC_RESET, >> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets), >> +}; > [...] > > and here: > >> +static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = { >> + .resets = sc7280_pdc_resets, >> + .offset = RPMH_SC7280_PDC_SYNC_RESET, >> + .num_resets = ARRAY_SIZE(sc7280_pdc_resets), >> +}; > > [...] >> @@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct >> reset_controller_dev *rcdev, >> unsigned long idx) >> { >> struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev); >> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx]; >> >> - return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET, >> - BIT(sdm845_pdc_resets[idx].bit), >> - BIT(sdm845_pdc_resets[idx].bit)); >> + return regmap_update_bits(data->regmap, data->desc->offset, >> BIT(map->bit), BIT(map->bit)); >> } > > Why not go one step further: > > u32 mask = BIT(data->desc->resets[idx].bit); > > return regmap_update_bits(data->regmap, data->desc->offset, mask, > mask); > > That seems to be a common pattern in other qcom drivers. will send out a separate patch for the other reset driver. > Either way, with the above reset/num_reset changes: > > Reviewed-by: Philipp Zabel > > Also, > > Acked-by: Philipp Zabel > > for the whole series to go through the qcom tree, or let me know if you > want me to pick up patches 2-4 next round. > > regards > Philipp -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.