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Tue, 4 May 2021 23:38:01 -0700 Envelope-to: u.kleine-koenig@pengutronix.de, thierry.reding@gmail.com, lee.jones@linaro.org, alvaro.gamez@hazent.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, sean.anderson@seco.com Received: from [172.30.17.109] (port=46602) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1leBAX-00089z-Ma; Tue, 04 May 2021 23:38:01 -0700 Subject: Re: [PATCH v2 2/2] pwm: Add support for Xilinx AXI Timer To: Sean Anderson , , CC: , , , Alvaro Gamez , Lee Jones , Thierry Reding , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= References: <20210504184925.3399934-1-sean.anderson@seco.com> <20210504184925.3399934-2-sean.anderson@seco.com> From: Michal Simek Message-ID: Date: Wed, 5 May 2021 08:37:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <20210504184925.3399934-2-sean.anderson@seco.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 25194029-22f4-46ce-f903-08d90f9055de X-MS-TrafficTypeDiagnostic: MWHPR02MB3166: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: V/2HlHIePlZA5QLc+9TgvXSN0nQsMiuGC2KX6DeJj99+msLAdIj/cvfvglkTN15V57Oa5vke0j2YEIGJZoLdaYWuYMbSASR8CfYwpLOrtGS4/wRHf+DdOEhmiJQ1iHkYtYKTDFMigj57IGrVmr9fx7IECTJYJ9IgoFBGh+FoptjpXkpI+5ldoZVqYhj7xoXRMcnUvITW+hxdlJE3DHoGcPqZePIHKOGZl9UDW2dZcjYvCX3OKlAuoq5Erwmj6SPBrnfJ3c6hkkhOcFIrFC25TK1ToZ93rqUHS4wJu/fpkR8Sv5pZo24sbnJNgbszdAzMw6KM8j5XHOwUKPYbLJ4/lHPo6qphhaVs6ATLTSJorWRAwYb7nsXG+nb38QShmmvYZOfUWbtrt8F+wqcWKngTEbT+p3K7WSnJZO2ih4fnNGYb2dE2uDFzY+Fi4hvHsPKiKJrOpRDvHT6nfrwaDgQWoAB0jyyN3BGdiMPnVhZkRwpTKQ7s2LoM0G+5m8YO32+nLkTW0QM+5THYwcCzDh4DqNSBtzyb+P4A6QnN0JZ1whu8OiOqJVfS6guH50eMwer0qiCjw2cKIUhCwSJ3IHYYkO+vVSk6iF2CrnzZXZWpub44lS9Z1rQ2ixTS2IHL9uh1p+cpqCYmBFoA4/ht77M0moxdfHFG+mA8BDCuorz2MjL2EFXWO/n5dDfbqsjNydfTU+o9PUnLBSNbK/ksYlGvHdWSee4NFspVZvSm6IRv8OU0PD/CVOrV4tz5Yq42P66mh0Gk0DSuK46HccJkvcWab9SffvpCrWu5gdHfGmsVfQ0= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(39850400004)(136003)(376002)(346002)(396003)(46966006)(36840700001)(2616005)(54906003)(478600001)(8936002)(53546011)(70586007)(5660300002)(7636003)(70206006)(82740400003)(82310400003)(186003)(110136005)(36756003)(26005)(9786002)(44832011)(356005)(31696002)(47076005)(31686004)(36860700001)(2906002)(966005)(8676002)(336012)(36906005)(316002)(4326008)(83380400001)(426003)(50156003)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 06:38:03.9219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25194029-22f4-46ce-f903-08d90f9055de X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB3166 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/4/21 8:49 PM, Sean Anderson wrote: > This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly > found on Xilinx FPGAs. There is another driver for this device located > at arch/microblaze/kernel/timer.c, but it is only used for timekeeping. > This driver was written with reference to Xilinx DS764 for v1.03.a [1]. > > [1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf > > Signed-off-by: Sean Anderson > --- > I tried adding a XILINX_PWM_ prefix to all the defines, but IMO it > really hurt readability. That prefix almost doubles the size the > defines, and is particularly excessive in something like > XILINX_PWM_TCSR_RUN_MASK. > > Changes in v2: > - Don't compile this module by default for arm64 > - Add dependencies on COMMON_CLK and HAS_IOMEM > - Add comment explaining why we depend on !MICROBLAZE > - Add comment describing device > - Rename TCSR_(SET|CLEAR) to TCSR_RUN_(SET|CLEAR) > - Use NSEC_TO_SEC instead of defining our own > - Use TCSR_RUN_MASK to check if the PWM is enabled, as suggested by Uwe > - Cast dividends to u64 to avoid overflow > - Check for over- and underflow when calculating TLR > - Set xilinx_pwm_ops.owner > - Don't set pwmchip.base to -1 > - Check range of xlnx,count-width > - Ensure the clock is always running when the pwm is registered > - Remove debugfs file :l > - Report errors with dev_error_probe > > drivers/pwm/Kconfig | 13 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-xilinx.c | 301 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 315 insertions(+) > create mode 100644 drivers/pwm/pwm-xilinx.c Without looking below another driver which target the same IP is just wrong that's why NACK from me. Thanks, Michal