From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936186AbcIPQtb (ORCPT ); Fri, 16 Sep 2016 12:49:31 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:35346 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936146AbcIPQtV (ORCPT ); Fri, 16 Sep 2016 12:49:21 -0400 Subject: Re: [PATCH 2/2] phy: msm8996-pcie-phy: Add support to msm8996 pcie phy To: Stanimir Varbanov , Kishon Vijay Abraham I References: <1473245733-17260-1-git-send-email-srinivas.kandagatla@linaro.org> <1473245733-17260-3-git-send-email-srinivas.kandagatla@linaro.org> <2afe8523-925f-b538-f217-23ea7a267e11@linaro.org> Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org From: Srinivas Kandagatla Message-ID: Date: Fri, 16 Sep 2016 17:49:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <2afe8523-925f-b538-f217-23ea7a267e11@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/09/16 15:14, Stanimir Varbanov wrote: >> > + writel_relaxed(0x0f, base + QSERDES_COM_BG_TRIM); >> > + writel_relaxed(0x0f, base + QSERDES_COM_PLL_IVCO); >> > + writel_relaxed(0x19, base + QSERDES_COM_CLK_EP_DIV); >> > + writel_relaxed(0x10, base + QSERDES_COM_CLK_ENABLE1); >> > + writel_relaxed(0x00, base + QSERDES_COM_HSCLK_SEL); >> > + writel_relaxed(0x40, base + QSERDES_COM_RESCODE_DIV_NUM); >> > + writel_relaxed(0x00, base + PCIE_COM_SW_RESET); >> > + writel_relaxed(0x03, base + PCIE_COM_START_CONTROL); > I'd make an array with register/value pair and write the registers with > a for () loop. IMO it will be more readable. > > Probably 3 arrays - power_on, power_on_common and power_off. Thats good idea, I will keep that in mind before sending next version with common phy driver for USB/PCIE/UFS. thanks srini