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[24.9.64.241]) by smtp.gmail.com with ESMTPSA id x17sm5298087ilm.40.2021.02.26.13.55.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Feb 2021 13:55:17 -0800 (PST) Subject: Re: [PATCH] iommu/amd: Fix event counter availability check To: Paul Menzel , Alexander Monakov , Suravee Suthikulpanit Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, David Coe , Joerg Roedel , "Tj (Elloe Linux)" , Shuah Khan References: <20200529200738.1923-1-amonakov@ispras.ru> <4aba4c61-1878-3d4e-d52e-3ccac9715010@molgen.mpg.de> From: Shuah Khan Message-ID: Date: Fri, 26 Feb 2021 14:55:16 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <4aba4c61-1878-3d4e-d52e-3ccac9715010@molgen.mpg.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/26/21 2:44 PM, Paul Menzel wrote: > [cc: +suravee, +jörg] > > Dear Alex, dear Shuah, dear Suravee, dear Jörg, > > > Am 03.06.20 um 08:54 schrieb Alexander Monakov: >> On Tue, 2 Jun 2020, Shuah Khan wrote: >> >>> I changed the logic to read config to get max banks and counters >>> before checking if counters are writable and tried writing to all. >>> The result is the same and all of them aren't writable. However, >>> when disable the writable check and assume they are, I can run >> [snip] >> >> This is similar to what I did. I also noticed that counters can >> be successfully used with perf if the initial check is ignored. >> I was considering sending a patch to remove the check and adjust >> the event counting logic to use counters as read-only, but after >> a bit more investigation I've noticed how late pci_enable_device >> is done, and came up with this patch. It's a path of less resistance: >> I'd expect maintainers to be more averse to removing the check >> rather than fixing it so it works as intended (even though I think >> the check should not be there in the first place). >> >> However: >> >> The ability to modify the counters is needed only for sampling the >> events (getting an interrupt when a counter overflows). There's no >> code to do that for these AMD IOMMU counters. A solution I would >> prefer is to not write to those counters at all. It would simplify or >> even remove a bunch of code. I can submit a corresponding patch if >> there's general agreement this path is ok. >> >> What do you think? > > I like this idea. Suravee, Jörg, what do you think? > > Commit 6778ff5b21b (iommu/amd: Fix performance counter initialization) > delays the boot up to 100 ms, which is over 20 % on fast systems, and > also just a workaround, and does not seem to work always. The delay is > also not mentioned in the commit message. > > Sounds good to me. I can test this out on my system. thanks, -- Shuah