From: Vidya Sagar <vidyas@nvidia.com>
To: Kishon Vijay Abraham I <kishon@ti.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<catalin.marinas@arm.com>, <will.deacon@arm.com>,
<lorenzo.pieralisi@arm.com>, <jingoohan1@gmail.com>,
<gustavo.pimentel@synopsys.com>, <mperttunen@nvidia.com>,
<tiwai@suse.de>, <spujar@nvidia.com>, <skomatineni@nvidia.com>,
<liviu.dudau@arm.com>, <krzk@kernel.org>, <heiko@sntech.de>,
<horms+renesas@verge.net.au>, <olof@lixom.net>,
<maxime.ripard@bootlin.com>, <andy.gross@linaro.org>,
<bjorn.andersson@linaro.org>, <jagan@amarulasolutions.com>,
<enric.balletbo@collabora.com>, <ezequiel@collabora.com>,
<stefan.wahren@i2se.com>, <marc.w.gonzalez@free.fr>,
<l.stach@pengutronix.de>, <tpiepho@impinj.com>,
<hayashi.kunihiko@socionext.com>, <yue.wang@amlogic.com>,
<shawn.lin@rock-chips.com>, <xiaowei.bao@nxp.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>
Subject: Re: [PATCH 08/10] phy: tegra: Add PCIe PIPE2UPHY support
Date: Wed, 3 Apr 2019 16:15:25 +0530 [thread overview]
Message-ID: <e60c1bb8-2b30-50b0-4864-6e0db8797b2c@nvidia.com> (raw)
In-Reply-To: <ee9bba31-c9ac-9275-6f55-f71fea1a33a0@ti.com>
On 4/3/2019 1:35 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 26/03/19 8:43 PM, Vidya Sagar wrote:
>> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
>> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
>> For each PCIe lane of a controller, there is a P2U unit instantiated at
>> hardware level. This driver provides support for the programming required
>> for each P2U that is going to be used for a PCIe controller.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> drivers/phy/tegra/Kconfig | 7 ++
>> drivers/phy/tegra/Makefile | 1 +
>> drivers/phy/tegra/pcie-p2u-tegra194.c | 138 ++++++++++++++++++++++++++++++++++
>> 3 files changed, 146 insertions(+)
>> create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c
>>
>> diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
>> index a3b1de953fb7..1460c060fa70 100644
>> --- a/drivers/phy/tegra/Kconfig
>> +++ b/drivers/phy/tegra/Kconfig
>> @@ -6,3 +6,10 @@ config PHY_TEGRA_XUSB
>>
>> To compile this driver as a module, choose M here: the module will
>> be called phy-tegra-xusb.
>> +
>> +config PHY_TEGRA194_PCIE_P2U
>> + tristate "NVIDIA Tegra P2U PHY Driver"
>> + depends on ARCH_TEGRA
>
> COMPILE_TEST
Done.
>> + select GENERIC_PHY
>> + help
>> + Enable this to support the P2U (PIPE to UPHY) that is part of Tegra 19x SOCs.
>> diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
>> index 898589238fd9..f85b2c86643d 100644
>> --- a/drivers/phy/tegra/Makefile
>> +++ b/drivers/phy/tegra/Makefile
>> @@ -4,3 +4,4 @@ phy-tegra-xusb-y += xusb.o
>> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
>> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
>> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
>> +obj-$(CONFIG_PHY_TEGRA194_PCIE_P2U) += pcie-p2u-tegra194.o
>> diff --git a/drivers/phy/tegra/pcie-p2u-tegra194.c b/drivers/phy/tegra/pcie-p2u-tegra194.c
>> new file mode 100644
>> index 000000000000..bb2412ec4765
>> --- /dev/null
>> +++ b/drivers/phy/tegra/pcie-p2u-tegra194.c
>> @@ -0,0 +1,138 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * P2U (PIPE to UPHY) driver for Tegra T194 SoC
>> + *
>> + * Copyright (C) 2018 NVIDIA Corporation.
>
> 2019
Done.
>> + *
>> + * Author: Vidya Sagar <vidyas@nvidia.com>
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/of.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/delay.h>
>> +#include <linux/of_platform.h>
>> +#include <soc/tegra/bpmp-abi.h>
>> +
>> +#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
>> +#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
>> +#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
>> +#define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
>> +#define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)
>> +
>> +#define P2U_RX_DEBOUNCE_TIME 0xa4
>> +#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xFFFF
>> +#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
>> +
>> +struct tegra_p2u {
>> + void __iomem *base;
>> +};
>> +
>> +static int tegra_p2u_power_off(struct phy *x)
>> +{
>> + return 0;
>
> Empty phy_ops are not required.
Done.
>> +}
>> +
>> +static int tegra_p2u_power_on(struct phy *x)
>> +{
>> + u32 val;
>> + struct tegra_p2u *phy = phy_get_drvdata(x);
>> +
>> + val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
>> + val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
>> + val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
>> + writel(val, phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
>> +
>> + val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN4);
>> + val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
>> + writel(val, phy->base + P2U_PERIODIC_EQ_CTRL_GEN4);
>> +
>> + val = readl(phy->base + P2U_RX_DEBOUNCE_TIME);
>> + val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
>> + val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
>> + writel(val, phy->base + P2U_RX_DEBOUNCE_TIME);
>
> This looks more like a init configuration rather than power on.
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_p2u_init(struct phy *x)
>> +{
>> + return 0;
>> +}
>> +
>> +static int tegra_p2u_exit(struct phy *x)
>> +{
>> + return 0;
>> +}
>
> Empty functions are not required.
Done.
>> +
>> +static const struct phy_ops ops = {
>> + .init = tegra_p2u_init,
>> + .exit = tegra_p2u_exit,
>> + .power_on = tegra_p2u_power_on,
>> + .power_off = tegra_p2u_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int tegra_p2u_probe(struct platform_device *pdev)
>> +{
>> + struct tegra_p2u *phy;
>> + struct phy *generic_phy;
>> + struct phy_provider *phy_provider;
>> + struct device *dev = &pdev->dev;
>> + struct resource *res;
>> +
>> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
>> + if (!phy)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
>> + phy->base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(phy->base))
>> + return PTR_ERR(phy->base);
>> +
>> + platform_set_drvdata(pdev, phy);
>> +
>> + generic_phy = devm_phy_create(dev, NULL, &ops);
>> + if (IS_ERR(generic_phy))
>> + return PTR_ERR(generic_phy);
>> +
>> + phy_set_drvdata(generic_phy, phy);
>> +
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> + if (IS_ERR(phy_provider))
>> + return PTR_ERR(phy_provider);
>> +
>
> return PTR_ERR_OR_ZERO(phy_provider);
Done.
>> + return 0;
>> +}
>> +
>> +static int tegra_p2u_remove(struct platform_device *pdev)
>> +{
>> + return 0;
>> +}
>
> not required.
I think this is still required as this driver can be made as a module right?
>
> Thanks
> Kishon
>
next prev parent reply other threads:[~2019-04-03 10:45 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 15:13 [PATCH 00/10] Add Tegra194 PCIe support Vidya Sagar
2019-03-26 15:13 ` [PATCH 01/10] PCI: save pci_bus pointer in pcie_port structure Vidya Sagar
2019-03-26 15:13 ` [PATCH 02/10] PCI: perform dbi regs write lock towards the end Vidya Sagar
2019-03-26 15:13 ` [PATCH 03/10] PCI: dwc: Move config space capability search API Vidya Sagar
2019-03-28 12:33 ` Thierry Reding
2019-04-01 11:46 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 04/10] PCI: Add #defines for PCIe spec r4.0 features Vidya Sagar
2019-03-26 15:13 ` [PATCH 05/10] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-03-27 10:10 ` Jon Hunter
2019-03-27 10:53 ` Vidya Sagar
2019-03-28 13:15 ` Thierry Reding
2019-04-01 10:01 ` Vidya Sagar
2019-04-01 15:07 ` Thierry Reding
2019-04-02 11:41 ` Vidya Sagar
2019-04-02 14:35 ` Thierry Reding
2019-04-03 6:22 ` Vidya Sagar
2019-04-02 19:21 ` Bjorn Helgaas
2019-03-31 6:42 ` Rob Herring
2019-04-01 11:18 ` Vidya Sagar
2019-04-01 14:31 ` Thierry Reding
2019-04-02 9:16 ` Vidya Sagar
2019-04-02 14:20 ` Thierry Reding
2019-04-03 5:29 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-03-28 16:59 ` Thierry Reding
2019-04-01 12:37 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 07/10] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-03-26 15:13 ` [PATCH 08/10] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-03 8:05 ` Kishon Vijay Abraham I
2019-04-03 10:45 ` Vidya Sagar [this message]
2019-03-26 15:13 ` [PATCH 09/10] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-03-27 10:07 ` Jon Hunter
2019-03-29 20:52 ` Bjorn Helgaas
2019-04-02 7:17 ` Vidya Sagar
2019-04-02 14:14 ` Thierry Reding
2019-04-03 9:15 ` Vidya Sagar
2019-04-02 18:31 ` Bjorn Helgaas
2019-04-03 9:43 ` Vidya Sagar
2019-04-03 17:36 ` Bjorn Helgaas
2019-04-04 19:53 ` Vidya Sagar
2019-04-05 18:58 ` Bjorn Helgaas
2019-04-09 11:30 ` Vidya Sagar
2019-04-09 13:26 ` Bjorn Helgaas
2019-04-10 6:10 ` Vidya Sagar
2019-04-10 8:14 ` Liviu Dudau
2019-04-10 9:53 ` Vidya Sagar
2019-04-10 11:35 ` Liviu Dudau
2019-03-26 15:13 ` [PATCH 10/10] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-03-27 10:08 ` Jon Hunter
2019-03-27 10:12 ` Vidya Sagar
2019-03-27 12:26 ` Jon Hunter
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