From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753828AbdFMRz0 (ORCPT ); Tue, 13 Jun 2017 13:55:26 -0400 Received: from foss.arm.com ([217.140.101.70]:52100 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751802AbdFMRzZ (ORCPT ); Tue, 13 Jun 2017 13:55:25 -0400 Subject: Re: [PATCH 03/12] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 To: Mathieu Poirier References: <1497278211-5001-1-git-send-email-suzuki.poulose@arm.com> <1497278211-5001-4-git-send-email-suzuki.poulose@arm.com> <20170613175336.GC6392@xps15> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij From: Suzuki K Poulose Message-ID: Date: Tue, 13 Jun 2017 18:55:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170613175336.GC6392@xps15> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/06/17 18:53, Mathieu Poirier wrote: > On Mon, Jun 12, 2017 at 03:36:42PM +0100, Suzuki K Poulose wrote: >> As per coresight standards, PIDR2 register has the following format : >> >> [2-0] - JEP106_bits6to4 >> [3] - JEDEC, designer ID is specified by JEDEC. >> >> However some of the drivers only use mask of 0x3 for the PIDR2 leaving >> bits [3-2] unchecked, which could potentially match the component for >> a different device altogether. This patch fixes the mask and the >> corresponding id bits for the existing devices. >> >> Cc: Mathieu Poirier >> Cc: Linus Walleij >> Signed-off-by: Suzuki K Poulose >> --- >> I have not touched the TPIU ids for Ux500 (see commit: 4339b699), >> as I don't have a platform to fix/correct the ids. >> --- >> drivers/hwtracing/coresight/coresight-funnel.c | 4 ++-- >> drivers/hwtracing/coresight/coresight-replicator-qcom.c | 4 ++-- >> drivers/hwtracing/coresight/coresight-stm.c | 8 ++++---- >> drivers/hwtracing/coresight/coresight-tmc.c | 4 ++-- >> drivers/hwtracing/coresight/coresight-tpiu.c | 4 ++-- > > Any reason for not adding ETMv3 to the list? From what I see in the > documentation bit [2-0] need to 0b011 and the JEDEC bit is always 1. I don't have a platform to test it easily. Hence the exclusion. Same for etbv10. Suzuki