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From: Dinh Nguyen <>
To: "Clément Péron" <>,
	"Russell King" <>,
	"Florian Fainelli" <>,,
Subject: Re: [PATCH] ARM: debug: enable UART1 for socfpga Cyclone5
Date: Tue, 23 Oct 2018 09:04:01 -0500	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Hi Clément,

On 10/09/2018 06:28 AM, Clément Péron wrote:
> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5.

I'm not sure the need for this patch. Are there any cyclone5 based
boards that has UART1 as the debug uart? I see that all of them are
using UART0.


  reply	other threads:[~2018-10-23 14:04 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-09 11:28 Clément Péron
2018-10-23 14:04 ` Dinh Nguyen [this message]
2018-10-23 14:44   ` Clément Péron
2018-10-23 20:35     ` Dinh Nguyen
2018-10-24  6:51       ` Uwe Kleine-König
2018-10-24 14:11         ` Clément Péron
2018-10-25 14:57           ` Dinh Nguyen

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