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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q34sm15167431pja.22.2020.05.26.00.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2020 00:03:03 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features. Date: Tue, 26 May 2020 15:02:36 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [greentime.hu@sifive.com: add support for dynamic vlen] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c8527d770c98..5a68a926da68 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif void riscv_fill_hwcap(void) { @@ -73,4 +77,11 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.26.2