From: Jiahui Cen <cenjiahui@huawei.com>
To: John Garry <john.garry@huawei.com>, <linux-kernel@vger.kernel.org>
Cc: Wei Xu <xuwei5@hisilicon.com>, Arnd Bergmann <arnd@arndb.de>,
"Bjorn Helgaas" <bhelgaas@google.com>,
Andy Shevchenko <andy.shevchenko@gmail.com>,
<xieyingtai@huawei.com>,
"linuxarm@openeuler.org" <linuxarm@openeuler.org>
Subject: Re: [PATCH] lib/logic_pio: Fix overlap check for pio registery
Date: Mon, 18 Jan 2021 09:27:53 +0800 [thread overview]
Message-ID: <eaedbff6-fd4f-e01e-b14c-482e8dd6d382@huawei.com> (raw)
In-Reply-To: <643b5c84-3e94-4029-721b-34b79c1b3589@huawei.com>
Hi John,
On 2021/1/15 18:10, John Garry wrote:
> On 21/12/2020 13:04, Jiahui Cen wrote:
>>> On 21/12/2020 03:24, Jiahui Cen wrote:
>>>> Hi John,
>>>>
>>>> On 2020/12/18 18:40, John Garry wrote:
>>>>> On 18/12/2020 06:23, Jiahui Cen wrote:
>>>>>> Since the [start, end) is a half-open interval, a range with the end equal
>>>>>> to the start of another range should not be considered as overlapped.
>>>>>>
>>>>>> Signed-off-by: Jiahui Cen<cenjiahui@huawei.com>
>>>>>> ---
>>>>>> lib/logic_pio.c | 2 +-
>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/lib/logic_pio.c b/lib/logic_pio.c
>>>>>> index f32fe481b492..445d611f1dc1 100644
>>>>>> --- a/lib/logic_pio.c
>>>>>> +++ b/lib/logic_pio.c
>>>>>> @@ -57,7 +57,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
>>>>>> new_range->flags == LOGIC_PIO_CPU_MMIO) {
>>>>>> /* for MMIO ranges we need to check for overlap */
>>>>>> if (start >= range->hw_start + range->size ||
>>>>>> - end < range->hw_start) {
>>>>>> + end <= range->hw_start) {
>>>>> It looks like your change is correct, but should not really have an impact in practice since:
>>>>> a: BIOSes generally list ascending IO port CPU addresses
>>>>> b. there is space between IO port CPU address regions
>>>>>
>>>>> Have you seen a problem here?
>>>>>
>>>> No serious problem. I found it just when I was working on adding support of
>>>> pci expander bridge for Arm in QEMU. I found the IO window of some extended
>>>> root bus could not be registered when I inserted the extended buses' _CRS
>>>> info into DSDT table in the x86 way, which does not sort the buses.
>>>>
>>>> Though root buses should be sorted in QEMU, would it be better to accept
>>>> those non-ascending IO windows?
>>>>
>>> ok, so it seems that you have seen a real problem, and this issue is not just detected by code analysis.
>>>
>>>> BTW, for b, it seems to be no space between IO windows of different root buses
>>>> generated by EDK2. Or maybe I missed something obvious.
>>> I don't know about that. Anyway, your change looks ok.
>>>
>>> Reviewed-by: John Garry<john.garry@huawei.com>
>>>
>>> BTW, for your virt env, will there be requirement to unregister PCI MMIO ranges? Currently we don't see that in non-virt world.
>>>
>> Thanks for your review.
>>
>> And currently there is no such a requirement in my virt env.
>>
>
> I am not sure what happened to this patch, but I plan on sending some patches in this area soon - do you want me to include this one?
>
Sorry for replying late. It's appreciated if you can include this patch.
Thanks!
Jiahui
> Thanks,
> John
>
> .
next prev parent reply other threads:[~2021-01-18 1:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 6:23 [PATCH] lib/logic_pio: Fix overlap check for pio registery Jiahui Cen
2020-12-18 10:40 ` John Garry
2020-12-21 3:24 ` Jiahui Cen
2020-12-21 11:12 ` John Garry
2020-12-21 13:04 ` Jiahui Cen
2021-01-15 10:10 ` John Garry
2021-01-18 1:27 ` Jiahui Cen [this message]
2021-03-15 10:30 ` John Garry
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