From: Gabriel Fernandez <gabriel.fernandez@st.com>
To: "Radosław Pietrzyk" <radoslaw.pietrzyk@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Nicolas Pitre <nico@linaro.org>, Arnd Bergmann <arnd@arndb.de>,
Daniel Thompson <daniel.thompson@linaro.org>,
Andrea Merello <andrea.merello@gmail.com>,
<devicetree@vger.kernel.org>, <amelie.delaunay@st.com>,
<kernel@stlinux.com>, <olivier.bideau@st.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<ludovic.barre@st.com>, <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
Date: Tue, 8 Nov 2016 09:35:58 +0100 [thread overview]
Message-ID: <ebadfacf-73fb-01a6-791a-324daad5e695@st.com> (raw)
In-Reply-To: <CAFvLkMQxvo=2Ak033n2XkPgdDfU5DLCMF7dj487QFB0e7WceCQ@mail.gmail.com>
Hi Radosław
Many thanks for reviewing.
On 11/07/2016 03:57 PM, Radosław Pietrzyk wrote:
>> +static struct clk_hw *clk_register_pll_div(const char *name,
>> + const char *parent_name, unsigned long flags,
>> + void __iomem *reg, u8 shift, u8 width,
>> + u8 clk_divider_flags, const struct clk_div_table *table,
>> + struct clk_hw *pll_hw, spinlock_t *lock)
>> +{
>> + struct stm32f4_pll_div *pll_div;
>> + struct clk_hw *hw;
>> + struct clk_init_data init;
>> + int ret;
>> +
>> + /* allocate the divider */
>> + pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
>> + if (!pll_div)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + init.name = name;
>> + init.ops = &stm32f4_pll_div_ops;
>> + init.flags = flags;
> Maybe it's worth to have CLK_SET_RATE_PARENT here and the VCO clock
> should have CLK_SET_RATE_GATE flag and we can get rid of custom
> divider ops.
I don't want to offer the possibility to change the vco clock through
the divisor of the pll (only by a boot-loader or by DT).
e.g. if i make a set rate on lcd-tft clock, i don't want to change the
SAI frequencies.
I used same structure for internal divisors of the pll (p, q, r) and for
post divisors (plli2s-q-div, pllsai-q-div & pllsai-r-div).
That why the CLK_SET_RATE_PARENT flag is transmit by parameter.
These divisors are similar because we have to switch off the pll before
changing the rate.
>
>
>> -static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
>> +
>> +static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
>> + const struct stm32f4_pll_data *data, spinlock_t *lock)
>> {
>> - unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
>> + struct stm32f4_pll *pll;
>> + struct clk_init_data init = { NULL };
>> + void __iomem *reg;
>> + struct clk_hw *pll_hw;
>> + int ret;
>> +
>> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
>> + if (!pll)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + init.name = data->vco_name;
>> + init.ops = &stm32f4_pll_gate_ops;
>> + init.flags = CLK_IGNORE_UNUSED;
> CLK_SET_RATE_GATE here
>
> Moreover why not having VCO as a composite clock from gate and mult ?
Yes, that sounds a good idea.
> According to docs SAI VCO (don't know about I2S ) must be within
> certain range so clk_set_rate_range should be somewhere.
next prev parent reply other threads:[~2016-11-08 8:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-07 13:05 [PATCH 0/6] Add STM32F4 missing clocks gabriel.fernandez
2016-11-07 13:05 ` [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards gabriel.fernandez
2016-11-07 13:53 ` Daniel Thompson
2016-11-07 14:05 ` Gabriel Fernandez
2016-11-07 14:57 ` Radosław Pietrzyk
2016-11-08 8:35 ` Gabriel Fernandez [this message]
2016-11-08 8:52 ` Radosław Pietrzyk
2016-11-08 16:19 ` Gabriel Fernandez
2016-11-09 8:10 ` Radosław Pietrzyk
2016-11-09 9:51 ` Gabriel Fernandez
2016-11-07 13:05 ` [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board gabriel.fernandez
2016-11-07 13:55 ` Daniel Thompson
2016-11-07 14:06 ` Gabriel Fernandez
2016-11-07 13:05 ` [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock gabriel.fernandez
2016-11-07 13:58 ` Daniel Thompson
2016-11-07 14:14 ` Gabriel Fernandez
2016-11-07 13:05 ` [PATCH 4/6] clk: stm32f4: Add I2S clock gabriel.fernandez
2016-11-07 14:14 ` Daniel Thompson
2016-11-08 16:26 ` Gabriel Fernandez
2016-11-07 13:05 ` [PATCH 5/6] clk: stm32f4: Add SAI clocks gabriel.fernandez
2016-11-07 13:05 ` [PATCH 6/6] arm: dts: stm32f4: Add external I2S clock gabriel.fernandez
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