From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751690AbdF1Ozy (ORCPT ); Wed, 28 Jun 2017 10:55:54 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:56041 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751526AbdF1Ozs (ORCPT ); Wed, 28 Jun 2017 10:55:48 -0400 Subject: Re: [PATCH v2 1/2] drivers/watchdog: Add optional ASPEED device tree properties To: Guenter Roeck References: <20170627211734.60477-1-cbostic@linux.vnet.ibm.com> <20170627211734.60477-2-cbostic@linux.vnet.ibm.com> <20170627213216.GA4132@roeck-us.net> <6f2a77e0-e64c-70b7-812a-6a5e8a0b5e6f@linux.vnet.ibm.com> <20170627220740.GA19461@roeck-us.net> Cc: wim@iguana.be, robh+dt@kernel.org, mark.rutland@arm.com, joel@jms.id.au, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org From: Christopher Bostic Date: Wed, 28 Jun 2017 09:55:41 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.11; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <20170627220740.GA19461@roeck-us.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 17062814-0040-0000-0000-0000036FFEF5 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007290; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00879947; UDB=6.00438616; IPR=6.00660101; BA=6.00005445; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015992; XFM=3.00000015; UTC=2017-06-28 14:55:45 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17062814-0041-0000-0000-000007641DA4 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-28_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706280244 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/27/17 5:07 PM, Guenter Roeck wrote: > On Tue, Jun 27, 2017 at 04:42:24PM -0500, Christopher Bostic wrote: >> >> On 6/27/17 4:32 PM, Guenter Roeck wrote: >>> On Tue, Jun 27, 2017 at 04:17:33PM -0500, Christopher Bostic wrote: >>>> Describe device tree optional properties: >>>> >>>> * aspeed,arm-reet - ARM CPU reset on signal >>>> * aspeed,soc-reset - SOC reset on signal >>>> * aspeed,sys-reset - System reset on signal >>>> Disabling system reset may be required in situations where >>>> one of the other watchdog engines in the system is responsible >>>> for this. >>>> * aspeed,interrupt - Interrupt CPU on signal >>>> * aspeed,external-signal - Generate external signal (WDT1 and WDT2 only) >>>> * aspeed,alt-boot - Boot from alternate block on signal >>>> >>>> Signed-off-by: Christopher Bostic >>>> --- >>>> v2 - Add 'aspeed,' prefix to all optional properties >>>> - Add arm-reset, soc-reset, interrupt, alt-boot properties >>>> --- >>>> .../devicetree/bindings/watchdog/aspeed-wdt.txt | 25 ++++++++++++++++++++++ >>>> 1 file changed, 25 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt >>>> index c5e74d7..555b8b4 100644 >>>> --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt >>>> +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt >>>> @@ -8,9 +8,34 @@ Required properties: >>>> - reg: physical base address of the controller and length of memory mapped >>>> region >>>> +Optional properties: >>>> + Signal behavior - Whenever a timeout occurs, the watchdog can be programmed >>>> + to generate 6 types of signals: >>>> + >>>> + - aspeed,arm-reset: If property is present then reset ARM CPU only. >>>> + >>>> + - aspeed,soc-reset: If property is present then reset SOC. >>>> + >>>> + - aspeed,sys-reset: If property is present then reset the entire chip. >>>> + In cases where one of the other watchdog engines >>>> + in the system is responsible for system reset it >>>> + may be required to not specify this property. >>>> + >>>> + - aspeed,interrupt: If property is present then interrupt CPU. >>>> + >>>> + - aspeed,external-signal: If property is present then signal is sent to >>>> + external reset counter (only WDT1 and WDT2). >>>> + - aspeed,alt-boot: If property is present then boot from alternate block. >>>> + >>>> Example: >>>> wdt1: watchdog@1e785000 { >>>> compatible = "aspeed,ast2400-wdt"; >>>> reg = <0x1e785000 0x1c>; >>>> + aspeed,arm-reset; >>>> + aspeed,soc-reset; >>>> + aspeed,sys-reset; >>>> + aspeed,interrupt; >>>> + aspeed,external-signal; >>>> + aspeed,alt-boot; >>> Is that a bit mask or a value ? I would have thought that, >>> for example, a complete system reset would include the SoC reset, >>> and a SoC reset would include the ARM reset. Generating an >>> interrupt while at the same time resetting the system (or >>> part of it) doesn't seem to make much sense either. >> No these aren't bitmasks. The example was intended to indicate what could >> be used. >> In practice only a subset of each of these properties would make any sense. >> How >> would you suggest the example be formatted to convey that? Multiple examples >> I suppose. >> > I would just pick one (which is perfectly fine). After all, it is an example. > > Reminds me: Is there a default (eg the chip's default configuration) ? > In other words, what is expected to happen if none of the properties > is specified ? Default was to enable SOC reset (parameter aspeed,soc-reset) and system reset (aspeed,sys-reset). Based on your comments in patch v2 2/2 it would be necessary for backwards compatibility to preserve that default behavior. So it seems the optional parameters should be inverted for these: no-soc-reset, no-sys-reset. Thanks, Chris > Thanks, > Guenter >