From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <bert@biot.com>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic
Date: Tue, 6 Oct 2020 11:03:17 +0000 [thread overview]
Message-ID: <ed7e13a5-db3e-79ad-0cdc-d2875cef2d22@microchip.com> (raw)
In-Reply-To: <20201001063421.qcjdikj2tje3jn6k@ti.com>
On 10/1/20 9:34 AM, Pratyush Yadav wrote:
> So using an address width of 4 here is not necessarily the right thing
> to do. This change would break SMPT parsing for all flashes that use
> 3-byte addressing by default because SMPT parsing can involve register
> reads/writes. One such device is the Cypress S28HS flash. In fact, this
> was what prompted me to write the patch [0].
Do you refer to spi_nor_get_map_in_use()? addr width, dummy and opcode
are discovered when reading sfdp, we should be fine. If READ SFDP
requirements have changed for octal ddr, then we'll have to handle that
separately.
Cheers,
ta
next prev parent reply other threads:[~2020-10-06 11:03 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 23:56 [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic Bert Vermeulen
2020-10-01 6:34 ` Pratyush Yadav
2020-10-01 14:15 ` Tudor.Ambarus
2020-10-01 22:22 ` Bert Vermeulen
2020-10-02 7:50 ` David Laight
2020-10-04 21:12 ` Bert Vermeulen
2020-10-04 21:36 ` David Laight
2020-10-06 23:19 ` Joel Stanley
2020-10-06 11:03 ` Tudor.Ambarus [this message]
2020-10-06 11:19 ` Tudor.Ambarus
2020-10-06 11:40 ` Pratyush Yadav
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