From: Jianxin Pan <jianxin.pan@amlogic.com>
To: Stephen Boyd <sboyd@kernel.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: Yixun Lan <yixun.lan@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Carlo Caione <carlo@caione.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liang Yang <liang.yang@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Hanjie Lin <hanjie.lin@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>, <linux-clk@vger.kernel.org>,
<linux-amlogic@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v6 1/3] clk: meson: add emmc sub clock phase delay driver
Date: Sun, 4 Nov 2018 23:12:17 +0800 [thread overview]
Message-ID: <efb9f8e2-8937-2a0a-6f13-2c4ed66fd6e4@amlogic.com> (raw)
In-Reply-To: <154130056376.88331.17004780065573288593@swboyd.mtv.corp.google.com>
Hi Stephen,
Thanks for your review.
Please see me comments below.
On 2018/11/4 11:02, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-11-01 09:30:53)
>> diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c
>> new file mode 100644
>> index 0000000..83e74ed
>> --- /dev/null
>> +++ b/drivers/clk/meson/clk-phase-delay.c
>> @@ -0,0 +1,66 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
>> + *
>> + * Copyright (c) 2017 Baylibre SAS.
>> + * Author: Jerome Brunet <jbrunet@baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan <yixun.lan@amlogic.com>
>> + * Author: Jianxin Pan <jianxin.pan@amlogic.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include "clkc.h"
>> +
>> +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_clk_phase_delay_data *ph =
>> + meson_clk_get_phase_delay_data(clk);
>
> Nitpick: Do this after declaring variables because it splits a line.
OK. I will split the assignment into another line. Thank you.
>
>> + unsigned long period_ps, p, d;
>> + int degrees;
>> +
>> + p = meson_parm_read(clk->map, &ph->phase);
>> + degrees = p * 360 / (1 << (ph->phase.width));
>
> Nitpick: Remove useless parenthesis.
OK. I will remove them.
>
>> +
>> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
>
> Is the cast necessary?
Yes, the cast can be droped. NSEC_PER_SEC is already defined wit type long.
>
>> + clk_hw_get_rate(hw));
>> +
>> + d = meson_parm_read(clk->map, &ph->delay);
>> + degrees += d * ph->delay_step_ps * 360 / period_ps;
>> + degrees %= 360;
>> +
>> + return degrees;
>> +}
>> +
>> +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_clk_phase_delay_data *ph =
>> + meson_clk_get_phase_delay_data(clk);
>> + unsigned long period_ps, d = 0, r;
>> + u64 p;
>> +
>> + p = degrees % 360;
>
> We don't allow phase to be larger than 360 so this isn't needed.
OK, Thank you.
>
>> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
>
> Drop the cast?
OK.
>
>> + clk_hw_get_rate(hw));
>> +
>> + /* First compute the phase index (p), the remainder (r) is the
>
> Nitpick: Please leave /* on it's own line.
OK.
>
>> + * part we'll try to acheive using the delays (d).
>> + */
>> + r = do_div(p, 360 / (1 << (ph->phase.width)));
>
> Drop useless parenthesis please.
OK, I will fix it. Thank you.
>
>> + d = DIV_ROUND_CLOSEST(r * period_ps,
>> + 360 * ph->delay_step_ps);
>> + d = min(d, PMASK(ph->delay.width));
>> +
>> + meson_parm_write(clk->map, &ph->phase, p);
>> + meson_parm_write(clk->map, &ph->delay, d);
>> + return 0;
>> +}
>
> .
>
next prev parent reply other threads:[~2018-11-04 15:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 16:30 [PATCH v6 0/3] clk: meson: add a sub EMMC clock controller support Jianxin Pan
2018-11-01 16:30 ` [PATCH v6 1/3] clk: meson: add emmc sub clock phase delay driver Jianxin Pan
2018-11-04 3:02 ` Stephen Boyd
2018-11-04 15:12 ` Jianxin Pan [this message]
2018-11-01 16:30 ` [PATCH v6 2/3] clk: meson: add DT documentation for emmc clock controller Jianxin Pan
2018-11-01 16:30 ` [PATCH v6 3/3] clk: meson: add sub MMC clock controller driver Jianxin Pan
2018-11-01 18:16 ` Martin Blumenstingl
2018-11-03 7:29 ` Jianxin Pan
2018-11-02 13:05 ` jbrunet
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