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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>, coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, tamas.zsoldos@arm.com,
	al.grant@arm.com, leo.yan@linaro.org, mike.leach@linaro.org,
	mathieu.poirier@linaro.org, jinlmao@qti.qualcomm.com
Subject: Re: [PATCH v2 08/10] coresight: trbe: Unify the enabling sequence
Date: Fri, 30 Jul 2021 11:10:40 +0530	[thread overview]
Message-ID: <f24ad9f5-f26a-c49c-2d43-dd3c8c1a4772@arm.com> (raw)
In-Reply-To: <20210723124611.3828908-9-suzuki.poulose@arm.com>



On 7/23/21 6:16 PM, Suzuki K Poulose wrote:
> Unify the sequence of enabling the TRBE. We do this from
> event_start and also from the TRBE IRQ handler. Lets move
> this to a common helper. The only minor functional change
> is returning an error when we fail to enable the TRBE.
> This should be handled already.
> 
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 34 +++++++++++---------
>  1 file changed, 18 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index d50f142e86d1..6d6aad171c72 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -632,6 +632,20 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>  	return size;
>  }
>  
> +static int __arm_trbe_enable(struct trbe_buf *buf,
> +			     struct perf_output_handle *handle)
> +{
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return -ENOSPC;
> +	}
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> +	trbe_enable_hw(buf);
> +	return 0;
> +}
> +
>  static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
>  {
>  	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> @@ -648,14 +662,8 @@ static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)

There is this (now) redundant assignment which needs to be dropped.

*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;

>  	cpudata->buf = buf;
>  	cpudata->mode = mode;
>  	buf->cpudata = cpudata;> -	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> -	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> -	if (buf->trbe_limit == buf->trbe_base) {
> -		trbe_stop_and_truncate_event(handle);
> -		return 0;
> -	}
> -	trbe_enable_hw(buf);
> -	return 0;
> +
> +	return __arm_trbe_enable(buf, handle);
>  }
>  
>  static int arm_trbe_disable(struct coresight_device *csdev)
> @@ -722,14 +730,8 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
>  		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>  		return;
>  	}
> -	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> -	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> -	if (buf->trbe_limit == buf->trbe_base) {
> -		trbe_stop_and_truncate_event(handle);
> -		return;
> -	}
> -	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> -	trbe_enable_hw(buf);
> +
> +	__arm_trbe_enable(buf, handle);
>  }
>  
>  static bool is_perf_trbe(struct perf_output_handle *handle)
> 
With that, this clean up makes sense.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

  reply	other threads:[~2021-07-30  5:39 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-23 12:46 [PATCH v2 00/10] coresight: TRBE and Self-Hosted trace fixes Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 01/10] coresight: etm4x: Save restore TRFCR_EL1 Suzuki K Poulose
2021-07-30  3:05   ` Anshuman Khandual
2021-07-23 12:46 ` [PATCH v2 02/10] coresight: etm4x: Use Trace Filtering controls dynamically Suzuki K Poulose
2021-07-30  3:48   ` Anshuman Khandual
2021-07-30 11:29     ` Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 03/10] coresight: etm-pmu: Ensure the AUX handle is valid Suzuki K Poulose
2021-07-30  4:14   ` Anshuman Khandual
2021-07-23 12:46 ` [PATCH v2 04/10] coresight: trbe: Ensure the format flag is set on truncation Suzuki K Poulose
2021-07-30  4:26   ` Anshuman Khandual
2021-07-30 11:37     ` Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 05/10] coresight: trbe: Drop duplicate TRUNCATE flags Suzuki K Poulose
2021-07-30  4:47   ` Anshuman Khandual
2021-07-30 12:58     ` Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 06/10] coresight: trbe: Fix handling of spurious interrupts Suzuki K Poulose
2021-07-30  5:15   ` Anshuman Khandual
2021-07-30 12:57     ` Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 07/10] coresight: trbe: Do not truncate buffer on IRQ Suzuki K Poulose
2021-07-26 12:34   ` Mike Leach
2021-07-26 16:01     ` Suzuki K Poulose
2021-07-27 10:46       ` Mike Leach
2021-07-27 13:06         ` Suzuki K Poulose
2021-07-28  9:25           ` Suzuki K Poulose
2021-07-23 12:46 ` [PATCH v2 08/10] coresight: trbe: Unify the enabling sequence Suzuki K Poulose
2021-07-30  5:40   ` Anshuman Khandual [this message]
2021-07-23 12:46 ` [PATCH v2 09/10] coresight: trbe: End the AUX handle on truncation Suzuki K Poulose
2021-07-30  5:54   ` Anshuman Khandual
2021-07-23 12:46 ` [PATCH v2 10/10] coresight: trbe: Prohibit trace before disabling TRBE Suzuki K Poulose
2021-07-30  6:58   ` Anshuman Khandual
2021-07-23 13:45 ` [PATCH v2 00/10] coresight: TRBE and Self-Hosted trace fixes Suzuki K Poulose

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