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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id r20sm19173224lfi.91.2020.01.21.08.57.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2020 08:57:55 -0800 (PST) Subject: Re: [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, broonie@kernel.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, spujar@nvidia.com, josephl@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> <1578986667-16041-23-git-send-email-skomatineni@nvidia.com> <9765b723-33af-9863-72c9-8094203c8cb8@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Tue, 21 Jan 2020 19:57:53 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <9765b723-33af-9863-72c9-8094203c8cb8@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 21.01.2020 19:19, Sowjanya Komatineni пишет: > > On 1/19/20 7:04 AM, Dmitry Osipenko wrote: >> External email: Use caution opening links or attachments >> >> >> 14.01.2020 10:24, Sowjanya Komatineni пишет: >> >> [snip] >> >>> diff --git a/drivers/clk/tegra/clk-tegra30.c >>> b/drivers/clk/tegra/clk-tegra30.c >>> index 5732fdbe20db..53d1c48532ae 100644 >>> --- a/drivers/clk/tegra/clk-tegra30.c >>> +++ b/drivers/clk/tegra/clk-tegra30.c >>> @@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[] >>> __initdata = { >>>        { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, >>>        { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 }, >>>        { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, >>> -     { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 }, >>> -     { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 }, >>> -     { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 }, >>> +     { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 }, >>> +     { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 }, >>>        { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, >>>        { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, >>>        { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, >>> >> What about to use the assigned-clock-rates in device-tree and thus to >> remove those PLL_A entries? > > Yes clock rates can be used and also PLL rate is set based on sample > rate during hw_params. So this can be removed. > > But PLLA clock rates are not related to this patch series and also > changing this needs audio function testing across all platforms and > currently we don't have audio functional tests in place for older > platforms. > > All audio clocks proper fixes and cleanup b/w clock driver and audio > driver will be done separately. If there are real plans to make sound driver to drive the PLLA rate, then indeed should be fine to keep it as-is for now.