* [PATCH v1 1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml
2021-06-24 11:47 [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
@ 2021-06-24 11:47 ` cl
2021-07-14 19:27 ` Rob Herring
2021-06-24 11:47 ` [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible cl
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: cl @ 2021-06-24 11:47 UTC (permalink / raw)
To: heiko
Cc: robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, lee.jones, Liang Chen
From: Liang Chen <cl@rock-chips.com>
add "rockchip,rk3568-pmu", "syscon", "simple-mfd" for pmu nodes on a
rk3568 platform to pmu.ymal.
Signed-off-by: Liang Chen <cl@rock-chips.com>
---
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
index 53115b92d17f..ceb15cea77e2 100644
--- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
@@ -23,6 +23,7 @@ select:
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
+ - rockchip,rk3568-pmu
required:
- compatible
@@ -35,6 +36,7 @@ properties:
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
+ - rockchip,rk3568-pmu
- const: syscon
- const: simple-mfd
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v1 1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml
2021-06-24 11:47 ` [PATCH v1 1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml cl
@ 2021-07-14 19:27 ` Rob Herring
0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2021-07-14 19:27 UTC (permalink / raw)
To: cl
Cc: robh+dt, linux-kernel, devicetree, lee.jones, jbx6244, heiko,
linux-rockchip, linux-arm-kernel, zhangqing
On Thu, 24 Jun 2021 19:47:17 +0800, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> add "rockchip,rk3568-pmu", "syscon", "simple-mfd" for pmu nodes on a
> rk3568 platform to pmu.ymal.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible
2021-06-24 11:47 [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
2021-06-24 11:47 ` [PATCH v1 1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml cl
@ 2021-06-24 11:47 ` cl
2021-07-14 19:32 ` Rob Herring
` (2 more replies)
2021-06-24 11:47 ` [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
` (2 subsequent siblings)
4 siblings, 3 replies; 11+ messages in thread
From: cl @ 2021-06-24 11:47 UTC (permalink / raw)
To: heiko
Cc: robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, lee.jones, Liang Chen
From: Liang Chen <cl@rock-chips.com>
Document rk3568 compatible for QoS registers.
Signed-off-by: Liang Chen <cl@rock-chips.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index f14ae6da0068..206f73ffc249 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -48,6 +48,7 @@ properties:
- rockchip,rk3066-qos
- rockchip,rk3288-qos
- rockchip,rk3399-qos
+ - rockchip,rk3568-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible
2021-06-24 11:47 ` [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible cl
@ 2021-07-14 19:32 ` Rob Herring
2021-07-14 19:57 ` Heiko Stübner
2021-07-15 11:15 ` Lee Jones
2 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2021-07-14 19:32 UTC (permalink / raw)
To: cl
Cc: linux-rockchip, robh+dt, zhangqing, jbx6244, linux-kernel,
devicetree, linux-arm-kernel, heiko, lee.jones
On Thu, 24 Jun 2021 19:47:18 +0800, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> Document rk3568 compatible for QoS registers.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible
2021-06-24 11:47 ` [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible cl
2021-07-14 19:32 ` Rob Herring
@ 2021-07-14 19:57 ` Heiko Stübner
2021-07-15 11:15 ` Lee Jones
2 siblings, 0 replies; 11+ messages in thread
From: Heiko Stübner @ 2021-07-14 19:57 UTC (permalink / raw)
To: cl, lee.jones
Cc: robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Liang Chen
Am Donnerstag, 24. Juni 2021, 13:47:18 CEST schrieb cl@rock-chips.com:
> From: Liang Chen <cl@rock-chips.com>
>
> Document rk3568 compatible for QoS registers.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
@Lee: I guess this one is yours :-)
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index f14ae6da0068..206f73ffc249 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -48,6 +48,7 @@ properties:
> - rockchip,rk3066-qos
> - rockchip,rk3288-qos
> - rockchip,rk3399-qos
> + - rockchip,rk3568-qos
> - samsung,exynos3-sysreg
> - samsung,exynos4-sysreg
> - samsung,exynos5-sysreg
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible
2021-06-24 11:47 ` [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible cl
2021-07-14 19:32 ` Rob Herring
2021-07-14 19:57 ` Heiko Stübner
@ 2021-07-15 11:15 ` Lee Jones
2 siblings, 0 replies; 11+ messages in thread
From: Lee Jones @ 2021-07-15 11:15 UTC (permalink / raw)
To: cl
Cc: heiko, robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
On Thu, 24 Jun 2021, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> Document rk3568 compatible for QoS registers.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568
2021-06-24 11:47 [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
2021-06-24 11:47 ` [PATCH v1 1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml cl
2021-06-24 11:47 ` [PATCH v1 2/3] dt-binding: mfd: syscon: add rk3568 QoS register compatible cl
@ 2021-06-24 11:47 ` cl
2021-06-24 12:51 ` Johan Jonker
2021-06-24 13:10 ` [RESEND PATCH " cl
2021-07-15 22:42 ` (subset) [PATCH v1 0/3] " Heiko Stuebner
4 siblings, 1 reply; 11+ messages in thread
From: cl @ 2021-06-24 11:47 UTC (permalink / raw)
To: heiko
Cc: robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, lee.jones, Liang Chen
From: Liang Chen <cl@rock-chips.com>
Add the power-management and QoS nodes to the core rk3568 dtsi.
Signed-off-by: Liang Chen <cl@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++
1 file changed, 229 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d225e6a45d5c..2737f26775ff 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
@@ -257,6 +258,234 @@
status = "disabled";
};
+ pmu: power-management@fdd90000 {
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3568-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+ power-domain@RK3568_PD_GPU {
+ reg = <RK3568_PD_GPU>;
+ clocks = <&cru ACLK_GPU_PRE>,
+ <&cru PCLK_GPU_PRE>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@RK3568_PD_VI {
+ reg = <RK3568_PD_VI>;
+ clocks = <&cru HCLK_VI>,
+ <&cru PCLK_VI>;
+ pm_qos = <&qos_isp>,
+ <&qos_vicap0>,
+ <&qos_vicap1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VO {
+ reg = <RK3568_PD_VO>;
+ clocks = <&cru HCLK_VO>,
+ <&cru PCLK_VO>,
+ <&cru ACLK_VOP_PRE>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_vop_m0>,
+ <&qos_vop_m1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RGA {
+ reg = <RK3568_PD_RGA>;
+ clocks = <&cru HCLK_RGA_PRE>,
+ <&cru PCLK_RGA_PRE>;
+ pm_qos = <&qos_ebc>,
+ <&qos_iep>,
+ <&qos_jpeg_dec>,
+ <&qos_jpeg_enc>,
+ <&qos_rga_rd>,
+ <&qos_rga_wr>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VPU {
+ reg = <RK3568_PD_VPU>;
+ clocks = <&cru HCLK_VPU_PRE>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVDEC {
+ clocks = <&cru HCLK_RKVDEC_PRE>;
+ reg = <RK3568_PD_RKVDEC>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVENC {
+ reg = <RK3568_PD_RKVENC>;
+ clocks = <&cru HCLK_RKVENC_PRE>;
+ pm_qos = <&qos_rkvenc_rd_m0>,
+ <&qos_rkvenc_rd_m1>,
+ <&qos_rkvenc_wr_m0>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_PIPE {
+ reg = <RK3568_PD_PIPE>;
+ clocks = <&cru PCLK_PIPE>;
+ pm_qos = <&qos_pcie2x1>,
+ <&qos_pcie3x1>,
+ <&qos_pcie3x2>,
+ <&qos_sata0>,
+ <&qos_sata1>,
+ <&qos_sata2>,
+ <&qos_usb3_0>,
+ <&qos_usb3_1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ qos_gpu: qos@fe128000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe128000 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m0: qos@fe138080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138080 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m1: qos@fe138100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138100 0x0 0x20>;
+ };
+
+ qos_rkvenc_wr_m0: qos@fe138180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138180 0x0 0x20>;
+ };
+
+ qos_isp: qos@fe148000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148000 0x0 0x20>;
+ };
+
+ qos_vicap0: qos@fe148080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148080 0x0 0x20>;
+ };
+
+ qos_vicap1: qos@fe148100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148100 0x0 0x20>;
+ };
+
+ qos_vpu: qos@fe150000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe150000 0x0 0x20>;
+ };
+
+ qos_ebc: qos@fe158000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158000 0x0 0x20>;
+ };
+
+ qos_iep: qos@fe158100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158100 0x0 0x20>;
+ };
+
+ qos_jpeg_dec: qos@fe158180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158180 0x0 0x20>;
+ };
+
+ qos_jpeg_enc: qos@fe158200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158200 0x0 0x20>;
+ };
+
+ qos_rga_rd: qos@fe158280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158280 0x0 0x20>;
+ };
+
+ qos_rga_wr: qos@fe158300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158300 0x0 0x20>;
+ };
+
+ qos_npu: qos@fe180000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe180000 0x0 0x20>;
+ };
+
+ qos_pcie2x1: qos@fe190000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190000 0x0 0x20>;
+ };
+
+ qos_pcie3x1: qos@fe190080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190080 0x0 0x20>;
+ };
+
+ qos_pcie3x2: qos@fe190100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190100 0x0 0x20>;
+ };
+
+ qos_sata0: qos@fe190200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190200 0x0 0x20>;
+ };
+
+ qos_sata1: qos@fe190280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190280 0x0 0x20>;
+ };
+
+ qos_sata2: qos@fe190300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190300 0x0 0x20>;
+ };
+
+ qos_usb3_0: qos@fe190380 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190380 0x0 0x20>;
+ };
+
+ qos_usb3_1: qos@fe190400 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190400 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@fe198000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe198000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@fe1a8000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@fe1a8080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
+ };
+
+ qos_vop_m1: qos@fe1a8100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
+ };
+
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568
2021-06-24 11:47 ` [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
@ 2021-06-24 12:51 ` Johan Jonker
0 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2021-06-24 12:51 UTC (permalink / raw)
To: cl, heiko
Cc: robh+dt, zhangqing, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, lee.jones
Hi Liang,
The nodes without 'reg' are sort alphabetically.
Nodes with 'reg' are sort on reg number.
pmu: power-management@fdd90000 {}
sdmmc2: mmc @fe000000 {}
qos_gpu: qos @fe128000 {}
[..]
sdmmc0: mmc @fe2b0000 {}
Johan
On 6/24/21 1:47 PM, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> Add the power-management and QoS nodes to the core rk3568 dtsi.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++
> 1 file changed, 229 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index d225e6a45d5c..2737f26775ff 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3568-power.h>
> #include <dt-bindings/soc/rockchip,boot-mode.h>
> #include <dt-bindings/thermal/thermal.h>
>
> @@ -257,6 +258,234 @@
> status = "disabled";
> };
>
> + pmu: power-management@fdd90000 {
> + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
> + reg = <0x0 0xfdd90000 0x0 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3568-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* These power domains are grouped by VD_GPU */
> + power-domain@RK3568_PD_GPU {
> + reg = <RK3568_PD_GPU>;
> + clocks = <&cru ACLK_GPU_PRE>,
> + <&cru PCLK_GPU_PRE>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + /* These power domains are grouped by VD_LOGIC */
> + power-domain@RK3568_PD_VI {
> + reg = <RK3568_PD_VI>;
> + clocks = <&cru HCLK_VI>,
> + <&cru PCLK_VI>;
> + pm_qos = <&qos_isp>,
> + <&qos_vicap0>,
> + <&qos_vicap1>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_VO {
> + reg = <RK3568_PD_VO>;
> + clocks = <&cru HCLK_VO>,
> + <&cru PCLK_VO>,
> + <&cru ACLK_VOP_PRE>;
> + pm_qos = <&qos_hdcp>,
> + <&qos_vop_m0>,
> + <&qos_vop_m1>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_RGA {
> + reg = <RK3568_PD_RGA>;
> + clocks = <&cru HCLK_RGA_PRE>,
> + <&cru PCLK_RGA_PRE>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_jpeg_dec>,
> + <&qos_jpeg_enc>,
> + <&qos_rga_rd>,
> + <&qos_rga_wr>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_VPU {
> + reg = <RK3568_PD_VPU>;
> + clocks = <&cru HCLK_VPU_PRE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_RKVDEC {
> + clocks = <&cru HCLK_RKVDEC_PRE>;
> + reg = <RK3568_PD_RKVDEC>;
> + pm_qos = <&qos_rkvdec>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_RKVENC {
> + reg = <RK3568_PD_RKVENC>;
> + clocks = <&cru HCLK_RKVENC_PRE>;
> + pm_qos = <&qos_rkvenc_rd_m0>,
> + <&qos_rkvenc_rd_m1>,
> + <&qos_rkvenc_wr_m0>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3568_PD_PIPE {
> + reg = <RK3568_PD_PIPE>;
> + clocks = <&cru PCLK_PIPE>;
> + pm_qos = <&qos_pcie2x1>,
> + <&qos_pcie3x1>,
> + <&qos_pcie3x2>,
> + <&qos_sata0>,
> + <&qos_sata1>,
> + <&qos_sata2>,
> + <&qos_usb3_0>,
> + <&qos_usb3_1>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_gpu: qos@fe128000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe128000 0x0 0x20>;
> + };
> +
> + qos_rkvenc_rd_m0: qos@fe138080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138080 0x0 0x20>;
> + };
> +
> + qos_rkvenc_rd_m1: qos@fe138100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138100 0x0 0x20>;
> + };
> +
> + qos_rkvenc_wr_m0: qos@fe138180 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138180 0x0 0x20>;
> + };
> +
> + qos_isp: qos@fe148000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148000 0x0 0x20>;
> + };
> +
> + qos_vicap0: qos@fe148080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148080 0x0 0x20>;
> + };
> +
> + qos_vicap1: qos@fe148100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148100 0x0 0x20>;
> + };
> +
> + qos_vpu: qos@fe150000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe150000 0x0 0x20>;
> + };
> +
> + qos_ebc: qos@fe158000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158000 0x0 0x20>;
> + };
> +
> + qos_iep: qos@fe158100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158100 0x0 0x20>;
> + };
> +
> + qos_jpeg_dec: qos@fe158180 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158180 0x0 0x20>;
> + };
> +
> + qos_jpeg_enc: qos@fe158200 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158200 0x0 0x20>;
> + };
> +
> + qos_rga_rd: qos@fe158280 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158280 0x0 0x20>;
> + };
> +
> + qos_rga_wr: qos@fe158300 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158300 0x0 0x20>;
> + };
> +
> + qos_npu: qos@fe180000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe180000 0x0 0x20>;
> + };
> +
> + qos_pcie2x1: qos@fe190000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190000 0x0 0x20>;
> + };
> +
> + qos_pcie3x1: qos@fe190080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190080 0x0 0x20>;
> + };
> +
> + qos_pcie3x2: qos@fe190100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190100 0x0 0x20>;
> + };
> +
> + qos_sata0: qos@fe190200 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190200 0x0 0x20>;
> + };
> +
> + qos_sata1: qos@fe190280 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190280 0x0 0x20>;
> + };
> +
> + qos_sata2: qos@fe190300 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190300 0x0 0x20>;
> + };
> +
> + qos_usb3_0: qos@fe190380 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190380 0x0 0x20>;
> + };
> +
> + qos_usb3_1: qos@fe190400 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190400 0x0 0x20>;
> + };
> +
> + qos_rkvdec: qos@fe198000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe198000 0x0 0x20>;
> + };
> +
> + qos_hdcp: qos@fe1a8000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8000 0x0 0x20>;
> + };
> +
> + qos_vop_m0: qos@fe1a8080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8080 0x0 0x20>;
> + };
> +
> + qos_vop_m1: qos@fe1a8100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8100 0x0 0x20>;
> + };
> +
> sdmmc2: mmc@fe000000 {
> compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xfe000000 0x0 0x4000>;
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RESEND PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568
2021-06-24 11:47 [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
` (2 preceding siblings ...)
2021-06-24 11:47 ` [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
@ 2021-06-24 13:10 ` cl
2021-07-15 22:42 ` (subset) [PATCH v1 0/3] " Heiko Stuebner
4 siblings, 0 replies; 11+ messages in thread
From: cl @ 2021-06-24 13:10 UTC (permalink / raw)
To: heiko
Cc: robh+dt, jbx6244, zhangqing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, lee.jones, Liang Chen
From: Liang Chen <cl@rock-chips.com>
Add the power-management and QoS nodes to the core rk3568 dtsi.
Signed-off-by: Liang Chen <cl@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++
1 file changed, 229 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d225e6a45d5c..618849186c39 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
@@ -257,6 +258,99 @@
status = "disabled";
};
+ pmu: power-management@fdd90000 {
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3568-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+ power-domain@RK3568_PD_GPU {
+ reg = <RK3568_PD_GPU>;
+ clocks = <&cru ACLK_GPU_PRE>,
+ <&cru PCLK_GPU_PRE>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@RK3568_PD_VI {
+ reg = <RK3568_PD_VI>;
+ clocks = <&cru HCLK_VI>,
+ <&cru PCLK_VI>;
+ pm_qos = <&qos_isp>,
+ <&qos_vicap0>,
+ <&qos_vicap1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VO {
+ reg = <RK3568_PD_VO>;
+ clocks = <&cru HCLK_VO>,
+ <&cru PCLK_VO>,
+ <&cru ACLK_VOP_PRE>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_vop_m0>,
+ <&qos_vop_m1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RGA {
+ reg = <RK3568_PD_RGA>;
+ clocks = <&cru HCLK_RGA_PRE>,
+ <&cru PCLK_RGA_PRE>;
+ pm_qos = <&qos_ebc>,
+ <&qos_iep>,
+ <&qos_jpeg_dec>,
+ <&qos_jpeg_enc>,
+ <&qos_rga_rd>,
+ <&qos_rga_wr>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VPU {
+ reg = <RK3568_PD_VPU>;
+ clocks = <&cru HCLK_VPU_PRE>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVDEC {
+ clocks = <&cru HCLK_RKVDEC_PRE>;
+ reg = <RK3568_PD_RKVDEC>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVENC {
+ reg = <RK3568_PD_RKVENC>;
+ clocks = <&cru HCLK_RKVENC_PRE>;
+ pm_qos = <&qos_rkvenc_rd_m0>,
+ <&qos_rkvenc_rd_m1>,
+ <&qos_rkvenc_wr_m0>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_PIPE {
+ reg = <RK3568_PD_PIPE>;
+ clocks = <&cru PCLK_PIPE>;
+ pm_qos = <&qos_pcie2x1>,
+ <&qos_pcie3x1>,
+ <&qos_pcie3x2>,
+ <&qos_sata0>,
+ <&qos_sata1>,
+ <&qos_sata2>,
+ <&qos_usb3_0>,
+ <&qos_usb3_1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
@@ -271,6 +365,141 @@
status = "disabled";
};
+ qos_gpu: qos@fe128000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe128000 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m0: qos@fe138080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138080 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m1: qos@fe138100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138100 0x0 0x20>;
+ };
+
+ qos_rkvenc_wr_m0: qos@fe138180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138180 0x0 0x20>;
+ };
+
+ qos_isp: qos@fe148000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148000 0x0 0x20>;
+ };
+
+ qos_vicap0: qos@fe148080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148080 0x0 0x20>;
+ };
+
+ qos_vicap1: qos@fe148100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148100 0x0 0x20>;
+ };
+
+ qos_vpu: qos@fe150000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe150000 0x0 0x20>;
+ };
+
+ qos_ebc: qos@fe158000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158000 0x0 0x20>;
+ };
+
+ qos_iep: qos@fe158100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158100 0x0 0x20>;
+ };
+
+ qos_jpeg_dec: qos@fe158180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158180 0x0 0x20>;
+ };
+
+ qos_jpeg_enc: qos@fe158200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158200 0x0 0x20>;
+ };
+
+ qos_rga_rd: qos@fe158280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158280 0x0 0x20>;
+ };
+
+ qos_rga_wr: qos@fe158300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158300 0x0 0x20>;
+ };
+
+ qos_npu: qos@fe180000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe180000 0x0 0x20>;
+ };
+
+ qos_pcie2x1: qos@fe190000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190000 0x0 0x20>;
+ };
+
+ qos_pcie3x1: qos@fe190080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190080 0x0 0x20>;
+ };
+
+ qos_pcie3x2: qos@fe190100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190100 0x0 0x20>;
+ };
+
+ qos_sata0: qos@fe190200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190200 0x0 0x20>;
+ };
+
+ qos_sata1: qos@fe190280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190280 0x0 0x20>;
+ };
+
+ qos_sata2: qos@fe190300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190300 0x0 0x20>;
+ };
+
+ qos_usb3_0: qos@fe190380 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190380 0x0 0x20>;
+ };
+
+ qos_usb3_1: qos@fe190400 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190400 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@fe198000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe198000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@fe1a8000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@fe1a8080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
+ };
+
+ qos_vop_m1: qos@fe1a8100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
+ };
+
sdmmc0: mmc@fe2b0000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2b0000 0x0 0x4000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: (subset) [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568
2021-06-24 11:47 [PATCH v1 0/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568 cl
` (3 preceding siblings ...)
2021-06-24 13:10 ` [RESEND PATCH " cl
@ 2021-07-15 22:42 ` Heiko Stuebner
4 siblings, 0 replies; 11+ messages in thread
From: Heiko Stuebner @ 2021-07-15 22:42 UTC (permalink / raw)
To: cl
Cc: Heiko Stuebner, robh+dt, linux-arm-kernel, lee.jones, devicetree,
linux-kernel, jbx6244, linux-rockchip, zhangqing
On Thu, 24 Jun 2021 19:47:16 +0800, cl@rock-chips.com wrote:
> v1:
> 1. Document rk3568 compatible for pmu and qos nodes.
> 2. Add the power-management and qos nodes to the core rk3568 dtsi.
>
> Liang Chen (3):
> dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml
> dt-binding: mfd: syscon: add rk3568 QoS register compatible
> arm64: dts: rockchip: add pmu and qos nodes for rk3568
>
> [...]
Applied, thanks!
[1/3] dt-bindings: arm: rockchip: add rk3568 compatible string to pmu.yaml
commit: b1c64924df5d2caedb8714148ce177d3384dfafd
[3/3] arm64: dts: rockchip: add pmu and qos nodes for rk3568
commit: d178bed180ef7e7ac16d3c586fb7330b3cb8fc4d
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 11+ messages in thread