From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4307FC04AB4 for ; Tue, 14 May 2019 05:29:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DCEC208CA for ; Tue, 14 May 2019 05:29:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="DqVGD9Sp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726811AbfENF3m (ORCPT ); Tue, 14 May 2019 01:29:42 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18457 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbfENF3l (ORCPT ); Tue, 14 May 2019 01:29:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 22:28:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 May 2019 22:29:39 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 May 2019 22:29:39 -0700 Received: from [10.24.47.172] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 May 2019 05:29:34 +0000 Subject: Re: [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for CDM register check To: Rob Herring CC: Lorenzo Pieralisi , Bjorn Helgaas , Mark Rutland , Thierry Reding , Jon Hunter , Kishon Vijay Abraham I , Catalin Marinas , Will Deacon , Jingoo Han , Gustavo Pimentel , Mikko Perttunen , , , , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , , Manikanta Maddireddy , References: <20190424052004.6270-1-vidyas@nvidia.com> <20190424052004.6270-8-vidyas@nvidia.com> <20190426143247.GA25107@bogus> <031df2ca-27de-2388-5f23-078320203f5d@nvidia.com> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Tue, 14 May 2019 10:59:31 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557811740; bh=cqJjsaktR+J8Rzac06BPbRbkXCQMRbYeXEjs18+haNc=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=DqVGD9SpIGwB+ICy+zXbqihOzxwZF83U/SQ2oW9SUGBCiTUWbFM2evWjeZaNNRcXp OUdYxDyeRXV/BmgAiiVD8BOefyvDaY7i6G3qmcv8B1QWNg9oUGJEloYXLeAlR6GTP+ 5ft4GbFstcouTV1VmsB5acuJkkQpCXPpm4vYhS6kxxYf7AeOYnfOn77cwsU7UEU5BC qecBcnP7PkPZzkcP0DGTgZ5euLnpKNLHgMv25PXeahLET5puUlat8Tgp13WbKdDq3L cc4MwKxr2dL0MMXQGuzeZT8NQi4r0U/0uogEF/Q9Fd3KDRQCoVbAwAvbR2vJzBSjH8 j4wCRmXxcqTew== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/13/2019 8:45 PM, Rob Herring wrote: > On Tue, May 7, 2019 at 3:25 AM Vidya Sagar wrote: >> >> On 4/26/2019 8:02 PM, Rob Herring wrote: >>> On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote: >>>> Add support to enable CDM (Configuration Dependent Module) registers check >>>> for any data corruption. CDM registers include standard PCIe configuration >>>> space registers, Port Logic registers and iATU and DMA registers. >>>> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook >>>> Version 4.90a >>>> >>>> Signed-off-by: Vidya Sagar >>>> --- >>>> Changes since [v4]: >>>> * None >>>> >>>> Changes since [v3]: >>>> * None >>>> >>>> Changes since [v2]: >>>> * Changed flag name from 'cdm-check' to 'enable-cdm-check' >>>> * Added info about Port Logic and DMA registers being part of CDM >>>> >>>> Changes since [v1]: >>>> * This is a new patch in v2 series >>>> >>>> Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ >>>> 1 file changed, 5 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> index 5561a1c060d0..85b872c42a9f 100644 >>>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> @@ -34,6 +34,11 @@ Optional properties: >>>> - clock-names: Must include the following entries: >>>> - "pcie" >>>> - "pcie_bus" >>>> +- enable-cdm-check: This is a boolean property and if present enables >>> >>> This needs a vendor prefix. >> Why only for this? Since this whole file is for Synopsys DesignWare core based PCIe IP, >> I thought there is specific prefix required. Am I wrong? Also, CDM checking is a feature >> of IP and DWC based implementations can choose either to enable this feature at hardware level >> or not. And whoever enabled it at hardware level (like Tegra194) can set this flag to >> enable corresponding software support. > > TBC, I meant a Synopsys vendor prefix, not NVIDIA. > > Any property that's not from a common binding should have a vendor > prefix. That hasn't always happened, so we do have lots of examples > without. Ok. got it. I'm going to take care of this in V7 series. > > Rob >