From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C62C7618B for ; Tue, 23 Jul 2019 13:35:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ABBB622543 for ; Tue, 23 Jul 2019 13:35:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="AMuTTrK1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390297AbfGWNfL (ORCPT ); Tue, 23 Jul 2019 09:35:11 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18687 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725827AbfGWNfL (ORCPT ); Tue, 23 Jul 2019 09:35:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Jul 2019 06:35:06 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 23 Jul 2019 06:35:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 23 Jul 2019 06:35:09 -0700 Received: from [10.21.132.148] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Jul 2019 13:34:23 +0000 Subject: Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool To: Jose Abreu , Lars Persson , "Ilias Apalodimas" CC: Joao Pinto , Alexandre Torgue , Maxime Ripard , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , Chen-Yu Tsai , Maxime Coquelin , linux-tegra , Giuseppe Cavallaro , "David S . Miller" , "linux-arm-kernel@lists.infradead.org" References: <29dcc161-f7c8-026e-c3cc-5adb04df128c@nvidia.com> <20190722101830.GA24948@apalos> <11557fe0-0cba-cb49-0fb6-ad24792d4a53@nvidia.com>

<2ad7bf21-1f1f-db0f-2358-4901b7988b7d@nvidia.com> <8093e352-d992-e17f-7168-5afbd9d3fb3f@nvidia.com> From: Jon Hunter Message-ID: Date: Tue, 23 Jul 2019 14:34:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563888906; bh=7VGjRoH75ovO9tIALq3z4+jcrGznO3YZAKnO1R6So9M=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=AMuTTrK149cSqktaiZ4bEIPKimlBVpQ4fVOi13I6VxYM4K0Cutj0Sk5zDx47aQUjO uXn6mFEB7yRrK2dNZcrNtX/dqmF6A1fDsKy+3HQ9uAo8lylyysvAvYDhpF1MttzJBF ABZkEknLIseNf+x/OhKgrHXPEIGJ6Zzpfm5pBXtbA0VHWIL2WXBme8bepGHzwY3jy4 /qYdriH76TTHPiRM4jygGqUWSTXI7V83RwaehzDNPo3gfL5u8aiSlV6o8/0xCf8NBj dmZ3lZ4D/+zrCPFUSEhWeBXT03vU1IveZ7nBZQEbEKZrz69pcvHYNXXrcqh8yAw/cX R1R2GdOrCnEHg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/07/2019 13:51, Jose Abreu wrote: > From: Jon Hunter > Date: Jul/23/2019, 12:58:55 (UTC+00:00) > >> >> On 23/07/2019 11:49, Jose Abreu wrote: >>> From: Jon Hunter >>> Date: Jul/23/2019, 11:38:33 (UTC+00:00) >>> >>>> >>>> On 23/07/2019 11:07, Jose Abreu wrote: >>>>> From: Jon Hunter >>>>> Date: Jul/23/2019, 11:01:24 (UTC+00:00) >>>>> >>>>>> This appears to be a winner and by disabling the SMMU for the ethernet >>>>>> controller and reverting commit 954a03be033c7cef80ddc232e7cbdb17df735663 >>>>>> this worked! So yes appears to be related to the SMMU being enabled. We >>>>>> had to enable the SMMU for ethernet recently due to commit >>>>>> 954a03be033c7cef80ddc232e7cbdb17df735663. >>>>> >>>>> Finally :) >>>>> >>>>> However, from "git show 954a03be033c7cef80ddc232e7cbdb17df735663": >>>>> >>>>> + There are few reasons to allow unmatched stream bypass, and >>>>> + even fewer good ones. If saying YES here breaks your board >>>>> + you should work on fixing your board. >>>>> >>>>> So, how can we fix this ? Is your ethernet DT node marked as >>>>> "dma-coherent;" ? >>>> >>>> TBH I have no idea. I can't say I fully understand your change or how it >>>> is breaking things for us. >>>> >>>> Currently, the Tegra DT binding does not have 'dma-coherent' set. I see >>>> this is optional, but I am not sure how you determine whether or not >>>> this should be set. >>> >>> From my understanding it means that your device / IP DMA accesses are coherent regarding the CPU point of view. I think it will be the case if GMAC is not behind any kind of IOMMU in the HW arch. >> >> I understand what coherency is, I just don't know how you tell if this >> implementation of the ethernet controller is coherent or not. > > Do you have any detailed diagram of your HW ? Such as blocks / IPs > connection, address space wiring , ... Yes, this can be found in the Tegra X2 Technical Reference Manual [0]. Unfortunately, you need to create an account to download it. Jon [0] https://developer.nvidia.com/embedded/dlc/parker-series-trm -- nvpublic