From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752042AbcGXQYv (ORCPT ); Sun, 24 Jul 2016 12:24:51 -0400 Received: from regular1.263xmail.com ([211.150.99.137]:42844 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751340AbcGXQYt (ORCPT ); Sun, 24 Jul 2016 12:24:49 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-MAE-MAIL_UID: 005794ebc30ebbae@maes@1502c6cf85acfa44 X-MAE-ID: 223.6.254.61 X-RL-SENDER: william.wu@rock-chips.com X-LOGIN-NAME: william.wu@rock-chips.com X-SENDER-IP: 61.154.35.158 Subject: Re: [PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT To: =?UTF-8?Q?Heiko_St=c3=bcbner?= , Rob Herring , Felipe Balbi References: <1468486762-21960-1-git-send-email-william.wu@rock-chips.com> <1468486762-21960-4-git-send-email-william.wu@rock-chips.com> <20160716225715.GA27724@rob-hp-laptop> <1738306.cydkc9Pb90@diego> Cc: gregkh@linuxfoundation.org, linux-rockchip@lists.infradead.org, briannorris@google.com, dianders@google.com, kever.yang@rock-chips.com, huangtao@rock-chips.com, frank.wang@rock-chips.com, eddie.cai@rock-chips.com, John.Youn@synopsys.com, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, sergei.shtylyov@cogentembedded.com, mark.rutland@arm.com, devicetree@vger.kernel.org From: "William.wu" Message-ID: Date: Mon, 25 Jul 2016 00:24:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <1738306.cydkc9Pb90@diego> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Heiko, On 2016/7/17 18:28, Heiko Stübner wrote: > Am Samstag, 16. Juli 2016, 17:57:15 schrieb Rob Herring: >> On Thu, Jul 14, 2016 at 04:59:20PM +0800, William Wu wrote: >>> Add snps,phyif-utmi-width devicetree property to configure >>> the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY >>> interface is a hardware property, and it's platform dependent. >>> Normally,the PHYIF can be configured during coreconsultant. >> ^ >> space >> >>> But for some specific USB cores(e.g. rk3399 SoC DWC3), the >>> default PHYIF configuration value is fault, so we need to >>> reconfigure it by software. >>> >>> And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM >>> must be set to the corresponding value according to the >>> UTMI+ PHY interface. >>> >>> Signed-off-by: William Wu >>> --- >>> Changes in v7: >>> - remove quirk and use only one property to configure utmi (Heiko, Rob >>> Herring) >>> >>> Changes in v6: >>> - use '-' instead of '_' in dts (Rob Herring) >>> >>> Changes in v5: >>> - None >>> >>> Changes in v4: >>> - rebase on top of balbi testing/next, remove pdata (balbi) >>> >>> Changes in v3: >>> - None >>> >>> Changes in v2: >>> - add a quirk for phyif_utmi (balbi) >>> >>> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ >>> drivers/usb/dwc3/core.c | 25 >>> +++++++++++++++++++++++++ drivers/usb/dwc3/core.h >>> | 10 ++++++++++ >>> 3 files changed, 38 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt >>> b/Documentation/devicetree/bindings/usb/dwc3.txt index 020b0e9..00cc541 >>> 100644 >>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt >>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt >>> >>> @@ -47,6 +47,9 @@ Optional properties: >>> - snps,hird-threshold: HIRD threshold >>> - snps,hsphy_interface: High-Speed PHY interface selection between >>> "utmi" for> >>> UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value >>> 3. >>> >>> + - snps,phyif-utmi-width: the value to configure the core to support a >>> UTMI+ PHY + with an 8- or 16-bit interface. Value 8 select 8-bit >>> + interface, value 16 select 16-bit interface. >> Is 'phy_type = "utmi_wide"' not the same as 16-bit width? >> >> Again, I think this should be common. > after knowing that I need to look for that "utmi_wide", I think I'd agree. > > I found mention of that in usb/ci-hdrc-usb2.txt and usb/fsl-usb.txt and from > the coresponding code, I can see that they really mean the 16bit interface, > the Rockchip TRM as well as the spec [0] seems to call it UTMI+ but really > looks the same as utmi_wide. > > Interestingly, there is already generic code in drivers/usb/phy/of.c so that > property should probably move to devicetree/bindings/usb/generic.txt > as well. > > > Heiko > > [0] http://cache.nxp.com/files/corporate/doc/support_info/UTMI-PLUS-SPECIFICATION.pdf Thank you very much for your kindly help and helpful suggestion.:-D I quite agree with you about use ‘phy_type’ to config UTMI+ interface for DWC3 controller, and add the ‘phy_type’ property to devicetree/bindings/usb/generic.txt. So I shouldn't add a new dts property ‘snps,phyif-utmi-width’ here， and just use ‘phy_type’is enough. BTW, I think rk3399 UTMI+ isn't the same as ‘utmi_wide’. Because UTMI+ support both 8-bit data interface and 16-bit data interface, but refer to code in drivers/usb/phy/of.c and related driver，‘phy_type = "utmi_wide"’means 16-bits, 'phy_type = utmi' means 8-bits. Dear Felipe， how about your opinion about add ‘phy_type’ to config UTMI+ interface? Best Regards William wu > > > >