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From: Jon Masters <jcm@redhat.com>
To: Mark Salter <msalter@redhat.com>, Duc Dang <dhdang@apm.com>,
	Bjorn Helgaas <helgaas@kernel.org>
Cc: Rafael Wysocki <rafael@kernel.org>,
	Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-pci@vger.kernel.org,
	linux-arm <linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Tomasz Nowicki <tn@semihalf.com>, patches <patches@apm.com>
Subject: Re: [PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
Date: Thu, 1 Dec 2016 14:17:04 -0500	[thread overview]
Message-ID: <f4b949c0-f992-b0fb-5f23-f71cb1f9713e@redhat.com> (raw)
In-Reply-To: <1480604901.4751.17.camel@redhat.com>

On 12/01/2016 10:08 AM, Mark Salter wrote:
> On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote:

>> +static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
>> +{
>> +	struct acpi_device *adev = to_acpi_device(cfg->parent);
>> +	struct acpi_pci_root *root = acpi_driver_data(adev);
>> +	struct device *dev = cfg->parent;
>> +	struct xgene_pcie_port *port;
>> +	struct resource *csr;
>> +
>> +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
>> +	if (!port)
>> +		return -ENOMEM;
>> +
>> +	csr = &xgene_v1_csr_res[root->segment];
> 
> This hard-coded assumption that segment N uses controller N breaks
> for m400 where segment 0 is using controller 3.

This seems very fragile. So in addition to Bjorn's comment about not
trusting firmware provided data for the segment offset in the CSR list,
you will want to also determine the controller from the ACPI tree. The
existing code walks the ACPI hierarchy and finds the CSR that way.
Obviously, the goal is to avoid that in the latest incarnation, but you
could still determine which controller matches a given device.

Jon.

-- 
Computer Architect | Sent from my Fedora powered laptop

  reply	other threads:[~2016-12-01 19:17 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-30 23:42 [PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller Duc Dang
2016-12-01 15:08 ` Mark Salter
2016-12-01 19:17   ` Jon Masters [this message]
2016-12-01 19:58     ` Duc Dang
2016-12-01 18:33 ` Bjorn Helgaas
2016-12-01 19:20   ` Mark Salter
2016-12-01 19:26     ` Jon Masters
2016-12-01 19:41     ` Bjorn Helgaas
2016-12-01 22:10       ` Duc Dang
2016-12-01 22:31         ` Jon Masters
2016-12-01 23:07         ` Bjorn Helgaas
2016-12-01 23:22           ` Duc Dang
2016-12-02  4:08             ` Jon Masters
2016-12-02  6:31               ` Jon Masters
2016-12-02  7:34                 ` Duc Dang
2016-12-02  8:08                   ` Jon Masters
2016-12-02 23:39               ` Bjorn Helgaas
2016-12-03  0:33                 ` Jon Masters
2016-12-05 21:21                   ` Bjorn Helgaas
2016-12-06 19:46                     ` Jon Masters
2016-12-06 20:18                       ` Bjorn Helgaas
2016-12-06 20:23                         ` Jon Masters
2016-12-13 21:35                         ` Jon Masters
2016-12-03  7:06                 ` Duc Dang
2016-12-05 21:20                   ` Bjorn Helgaas
2016-12-05 21:40                     ` Duc Dang
2016-12-05 23:31                     ` Jon Masters
2016-12-02  2:27   ` [PATCH v4 1/1] " Duc Dang
2016-12-02  7:12     ` Jon Masters
2016-12-02  7:36       ` Duc Dang
2016-12-02  8:11         ` Jon Masters
2016-12-02 19:39           ` Duc Dang
2016-12-02 19:59             ` Jon Masters
2016-12-03 10:06             ` [SPCR] mmio32 iotype access requirements for X-Gene 8250(_dw) UART Jon Masters
2016-12-03 17:11               ` Graeme Gregory
2016-12-03 17:15               ` Mark Salter
2016-12-03 20:33                 ` Jon Masters
2016-12-04 10:35                   ` Duc Dang
2016-12-02 11:36     ` [PATCH v4 1/1] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller Graeme Gregory
2016-12-02  2:52   ` [PATCH v3] " Duc Dang
2016-12-05 21:53     ` Bjorn Helgaas
2016-12-05 22:09       ` Duc Dang

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