From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>,
Anil Varughese <aniljoy@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
Date: Tue, 29 Oct 2019 12:23:35 +0530 [thread overview]
Message-ID: <f67723d1-f778-8e9d-2476-89f7b5bae977@ti.com> (raw)
In-Reply-To: <20191023125735.4713-14-kishon@ti.com>
Hi Rob,
On 23/10/19 6:27 PM, Kishon Vijay Abraham I wrote:
> Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
> PHY but a wrapper used to configure some of the input signals to the
> SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
> SERDES]
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
Since you've reviewed the other patches posted after this one, wanted to check
if this somehow slipped out of your radar.
Thanks
Kishon
> ---
> .../bindings/phy/ti,phy-j721e-wiz.yaml | 159 ++++++++++++++++++
> 1 file changed, 159 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> new file mode 100644
> index 000000000000..8a1eccee6c1d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> @@ -0,0 +1,159 @@
> +# SPDX-License-Identifier: (GPL-2.0)
> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: TI J721E WIZ (SERDES Wrapper)
> +
> +maintainers:
> + - Kishon Vijay Abraham I <kishon@ti.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - ti,j721e-wiz-16g
> + - ti,j721e-wiz-10g
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 3
> + description: clock-specifier to represent input to the WIZ
> +
> + clock-names:
> + items:
> + - const: fck
> + - const: core_ref_clk
> + - const: ext_ref_clk
> +
> + num-lanes:
> + maxItems: 1
> + minimum: 1
> + maximum: 4
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + "#reset-cells":
> + const: 1
> +
> + ranges: true
> +
> + assigned-clocks:
> + maxItems: 2
> +
> + assigned-clock-parents:
> + maxItems: 2
> +
> +patternProperties:
> + "^pll[0|1]_refclk$":
> + type: object
> + description: |
> + WIZ node should have subnodes for each of the PLLs present in
> + the SERDES.
> +
> + "^cmn_refclk1?$":
> + type: object
> + description: |
> + WIZ node should have subnodes for each of the PMA common refclock
> + provided by the SERDES.
> +
> + "^refclk_dig$":
> + type: object
> + description: |
> + WIZ node should have subnode for refclk_dig to select the reference
> + clock source for the reference clock used in the PHY and PMA digital
> + logic.
> +
> + "^serdes@[0-9a-f]+$":
> + type: object
> + description: |
> + WIZ node should have '1' subnode for the SERDES. It could be either
> + Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
> + bindings specified in
> + Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
> + Torrent SERDES should follow the bindings specified in
> + Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> +
> +required:
> + - compatible
> + - power-domains
> + - clocks
> + - clock-names
> + - num-lanes
> + - "#address-cells"
> + - "#size-cells"
> + - "#reset-cells"
> +
> +examples:
> + - |
> + #include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> + wiz@5000000 {
> + compatible = "ti,j721e-wiz-16g";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
> + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
> + num-lanes = <2>;
> + #reset-cells = <1>;
> +
> + pll0_refclk {
> + clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
> + clock-output-names = "wiz1_pll0_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz1_pll0_refclk>;
> + assigned-clock-parents = <&k3_clks 293 13>;
> + };
> +
> + pll1_refclk {
> + clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
> + clock-output-names = "wiz1_pll1_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz1_pll1_refclk>;
> + assigned-clock-parents = <&k3_clks 293 0>;
> + };
> +
> + cmn_refclk {
> + clocks = <&wiz1_refclk_dig>;
> + clock-output-names = "wiz1_cmn_refclk";
> + #clock-cells = <0>;
> + };
> +
> + cmn_refclk1 {
> + clocks = <&wiz1_pll1_refclk>;
> + clock-output-names = "wiz1_cmn_refclk1";
> + #clock-cells = <0>;
> + };
> +
> + refclk_dig {
> + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
> + clock-output-names = "wiz0_refclk_dig";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz0_refclk_dig>;
> + assigned-clock-parents = <&k3_clks 292 11>;
> + };
> +
> + serdes@5000000 {
> + compatible = "cdns,ti,sierra-phy-t0";
> + reg-names = "serdes";
> + reg = <0x00 0x5000000 0x00 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + resets = <&serdes_wiz0 0>;
> + reset-names = "sierra_reset";
> + clocks = <&wiz0_cmn_refclk>, <&wiz0_cmn_refclk1>;
> + clock-names = "cmn_refclk", "cmn_refclk1";
> + };
> + };
>
next prev parent reply other threads:[~2019-10-29 6:54 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 12:57 [PATCH v2 00/14] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-10-29 18:59 ` Rob Herring
2019-10-30 5:36 ` Kishon Vijay Abraham I
2019-11-05 9:40 ` Anil Joy Varughese
2019-10-23 12:57 ` [PATCH v2 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 08/14] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 11/14] phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-10-29 6:53 ` Kishon Vijay Abraham I [this message]
2019-10-29 19:08 ` Rob Herring
2019-10-30 5:45 ` Kishon Vijay Abraham I
2019-10-30 19:26 ` Rob Herring
2019-10-31 4:41 ` Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
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